Digital circuit design challenges and opportunities in the era of nanoscale CMOS
Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
System technology co-optimization for advanced integration
Advanced integration and packaging will drive the scaling of computing systems in the next
decade. Diversity in performance, cost and scale of the emerging systems implies that …
decade. Diversity in performance, cost and scale of the emerging systems implies that …
Cell circuit and layout with linear finfet structures
ST Becker - US Patent 9,563,733, 2017 - Google Patents
(57) ABSTRACT A cell circuit and corresponding layout is disclosed to include linear-
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
Finfet transistor circuit
ST Becker, MC Smayling, D Gandhi, J Mali… - US Patent …, 2014 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts
ST Becker, MC Smayling - US Patent 8,258,547, 2012 - Google Patents
(57) ABSTRACT A restricted layout region includes a diffusion level layout including a
number of diffusion region layout shapes that de? ne at least one p-type diffusion region and …
number of diffusion region layout shapes that de? ne at least one p-type diffusion region and …
Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch
ST Becker, MC Smayling - US Patent 8,058,671, 2011 - Google Patents
(57) ABSTRACT A semiconductor device includes a Substrate portion that includes a
plurality of diffusion regions that include at least one p-type diffusion region and at least one …
plurality of diffusion regions that include at least one p-type diffusion region and at least one …
Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common …
ST Becker, MC Smayling - US Patent 8,035,133, 2011 - Google Patents
(57) ABSTRACT A semiconductor device includes a Substrate portion having a plurality of
diffusion regions defined in a non-symmetrical manner relative to a virtual line defined to …
diffusion regions defined in a non-symmetrical manner relative to a virtual line defined to …
Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through …
ST Becker, MC Smayling - US Patent 8,022,441, 2011 - Google Patents
(57) ABSTRACT A semiconductor device is disclosed as having a substrate portion that
includes a plurality of diffusion regions that include at least one p-type diffusion region and …
includes a plurality of diffusion regions that include at least one p-type diffusion region and …
Methods for defining contact grid in dynamic array architecture
J Hong, S Kornachuk, ST Becker - US Patent 8,225,261, 2012 - Google Patents
First and second virtual grates are defined as respective sets of parallel virtual lines
extending across a layout area in first and second perpendicular directions, respectively …
extending across a layout area in first and second perpendicular directions, respectively …
[图书][B] EDA for IC implementation, circuit design, and process technology
L Lavagno, L Scheffer, G Martin - 2018 - books.google.com
Presenting a comprehensive overview of the design automation algorithms, tools, and
methodologies used to design integrated circuits, the Electronic Design Automation for …
methodologies used to design integrated circuits, the Electronic Design Automation for …