A 10.8-to-37.4 Gb/s reference-less FD-less single-loop quarter-rate bang-bang clock and data recovery employing deliberate-current-mismatch wide-frequency …

L Wang, Y Chen, C Yang, X Zhao… - … on Circuits and …, 2023 - ieeexplore.ieee.org
This paper reports a reference-less frequency-detector-less single-loop bang-bang clock
and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current …

Adaptive Clock and Data Recovery for Asymmetric Triangular Frequency Modulation Profile

AM Zaki - 2019 IEEE Pacific Rim Conference on …, 2019 - ieeexplore.ieee.org
Clock and Data Recovery (CDR) is an important block in Serializer/Deserializer (SerDes)
systems used to recover the clock from the bitstream. With high data rates, the effect of …

A 0.01-mm2 1.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase

X Zhao, Y Chen, X Zheng, PI Mak… - 2021 IEEE MTT-S …, 2021 - ieeexplore.ieee.org
This paper reports a single-loop full-rate bang-bang clock and data recovery (BBCDR)
without both external reference and separate frequency detector. Specifically, our bang …

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Y Mao, Y Charlon, Y Leduc, G Jacquemod - Journal of Low Power …, 2024 - mdpi.com
In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28
nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology …

A 10.8-to-37.4 Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme

L Wang, Y Chen, C Yang, X Zhao… - 2022 29th IEEE …, 2022 - ieeexplore.ieee.org
A reference-less frequency-detector (FD)-less single-loop quarter-rate bang-bang clock and
data recovery circuit (BBCDR) achieves a wide frequency acquisition. By the virtue of the …

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase …

L Wang, Y Chen, C Yang, X Zhou… - … Journal of Circuit …, 2023 - Wiley Online Library
This paper reports a bang‐bang clock and data recovery circuit (BBCDR) with an ultra‐wide
capture range. The circuit exhibits automatic frequency capture and phase locking over a …

Means to Accelerate Transfer of Information Between Integrated Circuits

V Melikyan - Machine Learning-based Design and Optimization of …, 2023 - Springer
This chapter is devoted to the development of means in I/O blocks that will allow to increase
the frequency of the transmitted signal and to level the distorted signal. Effective approaches …

New design of an ultra low power CDR architecture using FDSOI 28 nm technology

Y Mao, Y Charlon, Y Leduc… - 2023 21st IEEE …, 2023 - ieeexplore.ieee.org
In this paper, a new structure of a ring oscillator is proposed to realize an Injection-Locked
Ring Oscillator (ILRO) and an Injection-Locked Clock Data Recovery (ILCDR). This circuit is …

A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-less Sub-sampling CDR with Beat Detection FLL in 28nm CMOS

W Park, J Jin, M Park, S Jung… - 2022 IEEE Asian Solid …, 2022 - ieeexplore.ieee.org
The primary role of a frequency-locked loop (FLL) is to match the frequency of the recovered
clock to the bit-rate clock frequency. Since a perfect match is impossible, there is always a …

Design of High-Speed and Low-Power Internal Display Interface

이광훈 - 2023 - s-space.snu.ac.kr
In this thesis, major concerns in the architecture of internal display interface are explained.
Considering the limited battery capacity of mobile phones and the increasing amount of …