Recent thermal management techniques for microprocessors

J Kong, SW Chung, K Skadron - ACM Computing Surveys (CSUR), 2012 - dl.acm.org
Microprocessor design has recently encountered many constraints such as power, energy,
reliability, and temperature. Among these challenging issues, temperature-related issues …

A survey of optimization techniques for thermal-aware 3D processors

K Cao, J Zhou, T Wei, M Chen, S Hu, K Li - Journal of Systems Architecture, 2019 - Elsevier
Interconnect scaling has become a major design challenge for traditional planar (2D)
integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers …

Survey of energy-cognizant scheduling techniques

S Zhuravlev, JC Saez, S Blagodurov… - … on Parallel and …, 2012 - ieeexplore.ieee.org
Execution time is no longer the only metric by which computational systems are judged. In
fact, explicitly sacrificing raw performance in exchange for energy savings is becoming a …

Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints

J Meng, K Kawakami, AK Coskun - Proceedings of the 49th Annual …, 2012 - dl.acm.org
3D multicore systems with stacked DRAM have the potential to boost system performance
significantly; however, this performance increase may cause 3D systems to exceed the …

Learning-based application-agnostic 3D NoC design for heterogeneous manycore systems

BK Joardar, RG Kim, JR Doppa… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
The rising use of deep learning and other big-data algorithms has led to an increasing
demand for hardware platforms that are computationally powerful, yet energy-efficient. Due …

Handling the problems and opportunities posed by multiple on-chip memory controllers

M Awasthi, DW Nellans, K Sudan… - Proceedings of the 19th …, 2010 - dl.acm.org
Modern processors such as Tilera's Tile64, Intel's Nehalem, and AMD's Opteron are
migrating memory controllers (MCs) on-chip, while maintaining a large, flat memory address …

Analysis of critical thermal issues in 3D integrated circuits

F Tavakkoli, S Ebrahimi, S Wang, K Vafai - International Journal of Heat …, 2016 - Elsevier
Several key attributes of a 3D integrated chip structure are analyzed in this work. Critical
features related to the effect of the size of the substrate, heat sink, device layer, through …

Throughput maximization for periodic real-time systems under the maximal temperature constraint

H Huang, V Chaturvedi, G Quan, J Fan… - ACM Transactions on …, 2014 - dl.acm.org
In this article, we study the problem of how to maximize the throughput of a periodic real-time
system under a given peak temperature constraint. We assume that different tasks in our …

Thermal-aware task scheduling for 3D multicore processors

X Zhou, J Yang, Y Xu, Y Zhang… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more
dies vertically with a dense, high-speed interface to increase the device density and reduce …

Thermal-aware scheduling in green data centers

MT Chaudhry, TC Ling, A Manzoor… - ACM Computing …, 2015 - dl.acm.org
Data centers can go green by saving electricity in two major areas: computing and cooling.
Servers in data centers require a constant supply of cold air from on-site cooling …