A priority based output arbiter for NoC router

CH Chan, KL Tsai, F Lai, SH Tsai - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
Network-on-Chip (NoC) is an on-chip communication method with good scalability and
reliability. One of the most important issues of NoC design is low transmission latency …

Node resource management for DSP applications on 3D network-on-chip architecture

I Anagnostopoulos, A Bartzas… - … Conference on Digital …, 2009 - ieeexplore.ieee.org
Emerging DSP applications have different latency, energy consumption and quality of
service (QoS) requirements. An implementation of such applications requires a large …

Design and implementation of a dynamic weight arbiter for networks-on-chip

Z Xu, S Zhang, W Ni, Y Yang… - 2014 4th IEEE International …, 2014 - ieeexplore.ieee.org
As there are unbalanced communications between each computing core in multi-core
system, a dynamic weight arbiter for networks-on-chip is designed and implemented in this …

Assessing routing behavior on on-chip-network

HN Nguyen, VD Ngo, HW Choi - … International Conference on …, 2006 - ieeexplore.ieee.org
Network-on-chip (NoC) is being proposed as a scalable and reusable communication
platform for future SoC applications. An important problem in NoC design is deciding the …

Deadlock free routing algorithm for minimizing data packet transmission in network on chip

K Somasundaram, J Plosila - … Journal of Embedded and Real-Time …, 2012 - igi-global.com
Network on chip (NoC) has been proposed as a solution for addressing the design
challenges of future high performance nanoscale architectures. In NoCs, the traditional …

The optimum network on chip architectures for video object plane decoder design

VD Ngo, HN Nguyen, HW Choi - International Symposium on Parallel and …, 2006 - Springer
Abstract On Chip Network (OCN) has been proposed as a new methodology for addressing
the design challenges of future massly integrated system in nanoscale. In this paper, three …

[引用][C] 基于动态权重仲裁的NoC 路由节点的设计

林微 - 中国集成电路, 2014

[引用][C] Temperature-aware platform optimizations for 2D and 3D networks-on-chip

I Anagnostopoulos, A Bartzas, D Soudris - … on computer aided design (ICCAD'07), 2007