Design of a high-performance router with distributed shared-buffer for load balancing for on-chip networks
M Rezaei-Zare, M Fathy, A Rezaei-Zare - Microelectronics Journal, 2023 - Elsevier
The rapid decrease in the nanoscale size has led to an increase in the density of transistors
on a chip [1]. Hence, a large number of processing cores are on a chip. Since the traditional …
on a chip [1]. Hence, a large number of processing cores are on a chip. Since the traditional …
[PDF][PDF] Discrete Firefly Algorithm for Optimizing Topology Generation and Core Mapping of Network-on-Chip.
S Parvathi, S Umamaheswari - Intelligent Automation & Soft …, 2022 - cdn.techscience.cn
Network-on-chip (NoC) proves to be the best alternative to replace the traditional bus-based
interconnection in Multi-Processor System on a Chip (MPSoCs). Irregular NoC topologies …
interconnection in Multi-Processor System on a Chip (MPSoCs). Irregular NoC topologies …