Typical embedded processors, such as Digital Signal Processors (DSPs), usually adopt
Very Long Instruction Word (VLIW) architecture to improve computing efficiency. The …

The efficiency of VLIW processors can be improved by reducing the energy consumption
associated with accessing the register-file. This paper presents an energy-aware register …

The currently available compilation techniques are for general computing and are not
optimized for physical layer computing in 5G micro base stations. In such cases, the …

RISC-V 指令集架构(Instruction Set Architecture, ISA) 作为一种新兴的精简ISA, 因免费, 开源,
自由等特点而得到快速发展. 由于国内外对RISC-V 的研究主要集中在硬件开发 …

Code generation (for VLIW processor architectures) consists of instruction scheduling and
register allocation. For instruction scheduling, a list scheduling heuristic is often used …

Protocol independent switch architecture (PISA) chips allow users to customize protocols
and functions according to specific requirements, which has practical significance in the field …

The data size and data feature under the current mainstream compilation schemes can be
diversified, formal methods are thus mandatory. However, in a micro base station, as an …

This paper presents a novel modulo scheduling method, which is called Expanded Iterative
Modulo Scheduling (EIMS). EIMS integrates an adaptive loop expansion mechanism, and …

Predication is a well-known alternative to conditional branching. However, the
implementation of predication is costly in terms of extending the instruction set of the …

This paper presents a novel modulo scheduling method, which is called Expanded Modulo
Scheduling (EMS). Unlike existing methods which regard loop unrolling and scheduling …