An Overview of Low-Power VLSI Design Methods for CMOS and CNTFET-Based Circuits

A Karthik, N Domala, GS Kumar - … International Conference on …, 2023 - ieeexplore.ieee.org
Currently, the power consumption is one of the major concerns in VLSI circuit design based
on CMOS (Complementary Metal Oxide Semiconductor) and CNTFET (Carbon Nano Tube …

Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems

P Nagarajan, NA Kumar, PV Ramana - International Journal of …, 2020 - World Scientific
The flip-flops are considered as major contributors to the power dissipation of the clocking
system, which is made up of the clock provision network and storage elements (latches, flip …

Digital CMOS VLSI Implementation and Assessment of Power Efficient Delay Flip-Flop Using Dynamic CMOS Logic for Low Power VLSI Systems

P Nagarajan, I Chandra, N Ashokkumar… - … on Smart Electronics …, 2024 - ieeexplore.ieee.org
Generally, the flip-flops are vital circuit and foremost power in considering various digital
VLSI circuits. In this work, a unique power effective flip-flop, named 5-Device count duple …

POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP

P NAGARAJAN, T KAVITHA, NA Kumar… - REVUE ROUMAINE …, 2023 - journal.iem.pub.ro
Flip-flops are the fundamental building blocks of the data path structure. It is a key
component of digital circuits and systems. This work offers an exclusive master-slave flip-flop …

[PDF][PDF] Efficient timing element design featuring low power vlsi application

P Nagarajan, T Kavitha… - International Journal of …, 2016 - researchgate.net
In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered
(DDNET) flip flop for Featuring Efficient low power applications. Several art of design …

CMOS VLSI Implementation of Implicit Pulsed Dual Edge Triggered Flip Flop using Pass Transistor Logic for Power Efficient Applications

P Nagarajan, N Ashokkumar… - 2024 4th …, 2024 - ieeexplore.ieee.org
In general, the flipflops are acting as a key circuit and major power intaking element in
several digital systems modeling. In this work, a new power efficient flipflop topology titled …

[PDF][PDF] A Review on low-Power VLSI CMOS and CNTFET Circuits

KK Gopathoti, SS Pendyala - academia.edu
Nowadays, power consumption is one of the primary considerations in the design of VLSI
(Very Large Scale Integration) circuits based on complementary metal oxide semiconductors …

Design and performance evaluation of explicit pulsed register element for low power VISI circuits

PJ Priyanka, K Batri - Advances in Natural and Applied Sciences, 2016 - go.gale.com
In this paper, a low power flip flop design featuring an explicit pulsed register element and
also different types of modified explicit pulsed register element is presented. The clock to the …