Memory dependence prediction is a fundamental technique to increase instruction-and
memory-level parallelism in out-of-order processors, which are crucial for high performance …

Applications running on out-of-order cores have benefited for decades of store-to-load
forwarding which accelerates communication of store values to loads of the same thread …

The performance gap between in-order (InO) and out-of-order (OoO) cores comes from the
ability to dynamically create highly optimized instruction issue schedules. In this work, we …

Some instructions have more impact on processor performance than others. Identification of
these critical instructions can be used to modify and improve instruction processing …

In an out-of-order core, the load queue (LQ), the store queue (SQ), and the store buffer (SB)
are responsible for ensuring: i) correct forwarding of stores to loads and ii) correct ordering …

As semiconductor processing techniques continue to scale down, transient faults, also
known as soft errors, are increasingly becoming a reliability threat to high-performance …

Out-of-order cores provide high performance at the cost of energy efficiency. Dynamic
scheduling is one of the major contributors to this: generating highly optimized issue …

To continue to improve processor performance, microarchitects seek to increase the
effective instruction level parallelism (ILP) that can be exploited in applications. A …

In this paper, we argue that, for a class of fine-grain, synchronization-intensive, parallel
workloads, it is advantageous to consolidate synchronization and communication as much …

Various memory consistency model implementations (eg, x86, SPARC) willfully allow a core
to see its own stores while they are in limbo, ie, executed (and perhaps retired) but not yet …