A survey of architectural techniques for managing process variation
S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …
slow down and even pause technological scaling, and mitigation of it is the way to continue …
Rowhammer: A retrospective
This retrospective paper describes the RowHammer problem in dynamic random access
memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 Conference …
memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 Conference …
Error characterization, mitigation, and recovery in flash-memory-based solid-state drives
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …
continuously increased and cost has continuously decreased over decades. This positive …
Computedram: In-memory compute using off-the-shelf drams
In-memory computing has long been promised as a solution to the" Memory Wall" problem.
Recent work has proposed using chargesharing on the bit-lines of a memory in order to …
Recent work has proposed using chargesharing on the bit-lines of a memory in order to …
EDEN: Enabling energy-efficient, high-performance deep neural network inference using approximate DRAM
The effectiveness of deep neural networks (DNN) in vision, speech, and language
processing has prompted a tremendous demand for energy-efficient high-performance DNN …
processing has prompted a tremendous demand for energy-efficient high-performance DNN …
Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
This paper introduces a new DRAM design that enables fast and energy-efficient bulk data
movement across subarrays in a DRAM chip. While bulk data movement is a key operation …
movement across subarrays in a DRAM chip. While bulk data movement is a key operation …
Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …
latency is defined by three fundamental operations that take place within the DRAM cell …
The RowHammer problem and other issues we may face as memory becomes denser
O Mutlu - Design, Automation & Test in Europe Conference & …, 2017 - ieeexplore.ieee.org
As memory scales down to smaller technology nodes, new failure mechanisms emerge that
threaten its correct operation. If such failure mechanisms are not anticipated and corrected …
threaten its correct operation. If such failure mechanisms are not anticipated and corrected …