[PDF][PDF] Inverted gate vedic multiplier in 90nm CMOS technology
CR Patel, VB Adishesha, V Urankar… - American Journal of …, 2020 - pdfs.semanticscholar.org
This paper proposes the design and implementation of an enhanced binary multiplication
technique. Vedic Mathematics is a system of mathematics that was discovered by Indian …
technique. Vedic Mathematics is a system of mathematics that was discovered by Indian …
Vedic Multiplier Using Carry look ahead adder
J Suryawanshi, D Gawade, N Tank… - … on Advances in …, 2022 - ieeexplore.ieee.org
Multiplier is one of the crucial blocks in many DSP applications. There are various multiplier
architectures which are in use, some among these are Booth, Modified booth, Array and …
architectures which are in use, some among these are Booth, Modified booth, Array and …