On reducing test data volume for circular scan architecture using modified shuffled shepherd optimization
M Jayabalan, E Srinivas, FH Shajin… - Journal of Electronic …, 2021 - Springer
In this manuscript, a novel test data compression (TDC) system is proposes for reducing a
test data volume (TDV) for circular scan (CS) architecture. A modified version of meta …
test data volume (TDV) for circular scan (CS) architecture. A modified version of meta …
A unified test data volume compression scheme for circular scan architecture using hosted cuckoo optimization
Test data volume (TDV) is the main issue for lessening the test data volume for system-on-a-
chip (SoC), lessening test time, average power, and peak power. Several optimization …
chip (SoC), lessening test time, average power, and peak power. Several optimization …
Design of low power multiplier with less area using quaternary carry increment adder for new-fangled processors
K Gavaskar, D Malathi, G Ravivarma… - Wireless Personal …, 2023 - Springer
Multiplication is one of the most basic processes, in digital signal processing applications.
To process the instructions, most processors require multiplication. Because multipliers are …
To process the instructions, most processors require multiplication. Because multipliers are …
A variant of long multiplication design with low power and area using modified 7: 3 compressor for biomedical applications
K Gavaskar, D Malathi, G Ravivarma, VK Devi… - Wireless Personal …, 2022 - Springer
A compressor is an applicable part that is broadly operated in VLSI circuits and its systems
that take part in an important role in high-speed systems. This article computes that the new …
that take part in an important role in high-speed systems. This article computes that the new …
3D 堆叠封装热阻矩阵研究
黄卫， 蒋涵， 张振越， 蒋玉齐， 朱思雄， 杨中磊 - 电子与封装, 2022 - ep.org.cn
针对多芯片热阻矩阵的研究模型大多基于多芯片组件模型, 多芯片为2D 封装类型, 而对3D
芯片堆叠模型的热阻矩阵研究较少. 以3D 芯片堆叠模型为例, 研究分析封装器件热阻扩散 …
芯片堆叠模型的热阻矩阵研究较少. 以3D 芯片堆叠模型为例, 研究分析封装器件热阻扩散 …