Exploring sub-20nm FinFET design with predictive technology models
Predictive MOSFET models are critical for early stage design-technology co-optimization
and circuit design research. In this work, Predictive Technology Model files for sub-20nm …
and circuit design research. In this work, Predictive Technology Model files for sub-20nm …
Two-Dimensional Pattern Formation Using Graphoepitaxy of PS-b-PMMA Block Copolymers for Advanced FinFET Device and Circuit Fabrication
Directed self-assembly (DSA) of lamellar phase block-co-polymers (BCPs) can be used to
form nanoscale line-space patterns. However, exploiting the potential of this process for …
form nanoscale line-space patterns. However, exploiting the potential of this process for …
Method of making a FinFET device
JCY Yin, CH Wu, KC Ting, KH Chen - US Patent 8,697,515, 2014 - Google Patents
BACKGROUND The semiconductor integrated circuit (IC) industry has experienced
exponential growth. Technological advances in IC materials and design have produced …
exponential growth. Technological advances in IC materials and design have produced …
GIDL in doped and undoped FinFET devices for low-leakage applications
P Kerber, Q Zhang, S Koswatta… - IEEE Electron Device …, 2012 - ieeexplore.ieee.org
Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped-and
undoped-channel FinFET devices through 3-D process and device simulations is presented …
undoped-channel FinFET devices through 3-D process and device simulations is presented …
3-D-TCAD-based parasitic capacitance extraction for emerging multigate devices and circuits
AN Bhoj, RV Joshi, NK Jha - IEEE transactions on very large …, 2013 - ieeexplore.ieee.org
In recent years, the multigate field-effect transistor (FET) has emerged as the most viable
contender for technology scaling down to the sub-10-nm nodes. The nonplanar nature of …
contender for technology scaling down to the sub-10-nm nodes. The nonplanar nature of …
Comparative study of novel u-shaped SOI FinFET against multiple-fin bulk/SOI FinFET
Superior scalability and better gate-to-channel capacitive coupling can be achieved with
adopting gate-all-around (GAA) device architecture. However, compared against FinFET …
adopting gate-all-around (GAA) device architecture. However, compared against FinFET …
Series resistance reduction in stacked nanowire FETs for 7-nm CMOS technology
Vertically stacked nanowire field effect transistors currently dominate the race to become
mainstream devices for 7-nm CMOS technology node. However, these devices are likely to …
mainstream devices for 7-nm CMOS technology node. However, these devices are likely to …
Fin width and bias dependence of the response of triple-gate MOSFETs to total dose irradiation
The total ionizing dose response of triple-gate MOSFETs is investigated for various fin
widths and bias conditions. Experiments and simulations are used to analyze the buildup of …
widths and bias conditions. Experiments and simulations are used to analyze the buildup of …
Fully depleted devices for designers: FDSOI and FinFETs
TB Hook - Proceedings of the IEEE 2012 Custom Integrated …, 2012 - ieeexplore.ieee.org
Technologies featuring fully depleted transistors are entering the mainstream for designs at
the 28nm, 20nm, and 14nm nodes. Although these devices have been the playground of …
the 28nm, 20nm, and 14nm nodes. Although these devices have been the playground of …
Method of making a FinFET device
JCY Yin, CH Wu, KC Ting, C Kuang-Hsin - US Patent 9,659,810, 2017 - Google Patents
The present disclosure provides many different embodi ments of fabricating a FinFET device
that provide one or more improvements over the prior art. In one embodiment, a method of …
that provide one or more improvements over the prior art. In one embodiment, a method of …