Junctionless transistor (JLT) which does not have a PN junction in the source-channel-drain
path, is reported to have a lower OFF-state current and therefore is more scalable to lower …

Interface trap charges originate in the semiconductor while, fabricating the device, which
occur due to the process, radiation stimulated impairments, leading to serious reliability …

The kink effect in a fully depleted silicon-on-insulator (SOI) tunnel field-effect transistor
(TFET) is studied and compared with the results for a SOI metal–oxide–semiconductor field …

This article examines the impact of various interface trap charges on silicon carbide-based
gate—stack, dual metal, surrounding gate, FET (4H-SiC-GSDM-SGFET). It has been …

In a vertical TFET structure, controllability over the gate is enhanced because of the
favorable electrostatic potential and tunneling under the entire gate region by preventing the …

This paper investigates the reliability of the selective buried oxide TFET δ p+ silicon-
germanium layer at the tunneling junction. The impact of various uniform and Gaussian trap …

This work is intended to design a quadrature phase shift keying (QPSK) system starting from
the device design, characterization and optimization which is then followed by the circuit …

This paper presents a hetero-dielectric dual tunnel diode (HD-DTD) TFET formed by p++
type highly doped L-shaped trench with hetero gate dielectric and its electrical parameters …

The field-effect transistor (FET) has become a key technology that has shaped electronic
applications in a wide range of industries. These transistors are the building blocks of …

This paper presents the reliability issues of Ferroelectric Dopant Segregated Schottky
Barrier TFET (Fe DS-SBTFET). The device has been optimized for various thickness of …