A driver of a multi-level signaling interface is provided. The driver may be configured reduce
noise in a multi-level signal (eg, a pulse amplitude modulation signal) generated by the …

(57) ABSTRACT A memory interface may include a transmitter that generates multi-level
signals. The transmitter may employ channel equalization to improve the quality and …

A memory interface may include a transmitter that generates multi-level signals made up of
symbols that convey multiple bits of data. The transmitter may include a first data path for a …

Methods, systems, and devices for improving uniformity between levels of a multi-level
signal are described. Tech niques are provided herein to unify peak-to-peak voltage …

A memory device determines an operation mode based on an external voltage. The memory
device includes a cell array including a plurality of memory cells; and a mode selector that …

Methods, systems, and devices for output impedance calibration for signaling are described.
Techniques are provided herein to adjust impedance levels associated with data transmitted …

(57) ABSTRACT A semiconductor device includes a plurality of pads, where an external
reference resistor is connected to a first one of the pads, an impedance calibrating unit …

Techniques are provided herein to increase a rate of data transfer across a large number of
channels in a memory device using multi-level signaling. Such multi-level signaling may be …

(Continued) Primary Examiner Freshteh N Aghdam (74) Attorney, Agent, or Firm—Holland &
Hart LLP (57) ABSTRACT Techniques are provided herein to increase a rate of data transfer …

A memory interface may include a transmitter that generates multi-level signals made up of
symbols that convey multiple bits of data. The transmitter may include a first data path for a …