Design for manufacturability and reliability in extreme-scaling VLSI
In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …
accordance with the Moore's law, and the semiconductor industry has followed this law as …
Design for manufacturing with emerging nanolithography
In this paper, we survey key design for manufacturing issues for extreme scaling with
emerging nanolithography technologies, including double/multiple patterning lithography …
emerging nanolithography technologies, including double/multiple patterning lithography …
Tool and method for eliminating multi-patterning conflicts
HL Lin, CC Hsu, YY Shen, WJ Yang… - US Patent …, 2013 - Google Patents
BACKGROUND In Semiconductor fabrication processes, the resolution of a photoresist
pattern begins to blur at about 45 nanometer (nm) half pitch. To continue to use fabrication …
pattern begins to blur at about 45 nanometer (nm) half pitch. To continue to use fabrication …
Layout decomposition approaches for double patterning lithography
In double patterning lithography (DPL) layout decomposition for 45 nm and below process
nodes, two features must be assigned opposite colors (corresponding to different …
nodes, two features must be assigned opposite colors (corresponding to different …
Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology
As technology continues to scale to 14nm node, Double Patterning Lithography (DPL) is
pushed to near its limit. Triple Patterning Lithography (TPL) is a considerable and natural …
pushed to near its limit. Triple Patterning Lithography (TPL) is a considerable and natural …
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography
As double patterning lithography (DPL) becomes the leading candidate for sub-30 nm
lithography process, we need a fast and lithography friendly decomposition framework. In …
lithography process, we need a fast and lithography friendly decomposition framework. In …
Detailed routing algorithms for advanced technology nodes
M Ahrens, M Gester, N Klewinghaus… - … on computer-aided …, 2014 - ieeexplore.ieee.org
We present algorithms for routing in advanced technology nodes, used by BonnRoute (BR)
to obtain efficient and almost design rule clean wire packings and pin access solutions …
to obtain efficient and almost design rule clean wire packings and pin access solutions …
Design and manufacturing process co-optimization in nano-technology (Designer Track Paper)
Newest manufacturing technologies with feature sizes smaller than 20nm and FinFET
devices have favored more restrictive design rules for manufacturability while suffering from …
devices have favored more restrictive design rules for manufacturability while suffering from …
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning
Self-aligned double patterning (SADP) is a promising manufacturing option for sub-22nm
technology nodes. Studies have shown that SADP provides better overlay control than …
technology nodes. Studies have shown that SADP provides better overlay control than …
TRIAD: A triple patterning lithography aware detailed router
TPL-friendly detailed routers require a systematic approach to detect TPL conflicts. However,
the complexity of conflict graph (CG) impedes directly detecting TPL conflicts in CG. This …
the complexity of conflict graph (CG) impedes directly detecting TPL conflicts in CG. This …