High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

D De Caro, AGM Strollo - … on Circuits and Systems I: Regular …, 2005 - ieeexplore.ieee.org
This paper presents new techniques to implement direct digital frequency synthesizers
(DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with …

Distributed time and carrier frequency synchronization for dense wireless networks

MA Alvarez, U Spagnolini - IEEE Transactions on Signal and …, 2018 - ieeexplore.ieee.org
Dense networks call for interconnectivity of a large number of devices, and in this context,
the diversity of interconnected devices introduces challenges to be considered for …

Novel approach to the design of direct digital frequency synthesizers based on linear interpolation

JMP Langlois, D Al-Khalili - … on Circuits and Systems II: Analog …, 2003 - ieeexplore.ieee.org
This paper presents a novel approach to the design of direct digital frequency synthesizers
(DDFSs) with phase-to-sinusoid amplitude conversion blocks based on linear interpolation …

Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis

JMP Langlois, D Al-Khalili - IEE Proceedings-Circuits, Devices and Systems, 2004 - IET
The authors present a review of phase to sine amplitude conversion (PSAC) techniques for
direct digital frequency synthesis (DDFS). Principles of DDFS are first considered, then …

Considerations for phase accumulator design for direct digital frequency synthesizers

DJ Betowski, V Beiu - International Conference on Neural …, 2003 - ieeexplore.ieee.org
This paper reviews the approach of using a direct digital frequency synthesizer (DDFS) to
generate high-resolution, fast switching frequencies for modern communication systems …

Direct digital-frequency synthesis by analog interpolation

A McEwan, S Collins - … Transactions on Circuits and Systems II …, 2006 - ieeexplore.ieee.org
A highly compact 9-bit CMOS direct digital synthesizer without read-only memory that
consumes 8 muW/MHz is described. The circuit is based upon a small nonlinear array of six …

[PDF][PDF] An optimization of CORDIC algorithm and FPGA implementation

R Xu, Z Jiang, H Huang, C Dong - Int. J. Hybrid Inf. Technol, 2015 - gvpress.com
Abstract ASIC and FPGA ASIC and FPGA are considered to be the ideal platform for special
fast calculations because of the hardware structure, and how to achieve computational …

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA

M Genovese, E Napoli, D De Caro, N Petra… - Integration, 2014 - Elsevier
Abstract The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely
implemented in communication or signal processing systems. The recent literature proposes …

Design techniques for direct digital synthesis circuits with improved frequency accuracy over wide frequency ranges

S Leitner, H Wang, S Tragoudas - Journal of Circuits, Systems and …, 2017 - World Scientific
Recently, there is increasing interest in impedance sensors for various applications. Direct
digital synthesis (DDS) circuits are commonly used in such sensor circuits for generating …

Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs

F Cardells-Tormo… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
This paper deals with an field-programmable gate array (FPGA)-implementation of
quadrature direct digital frequency synthesizers (QDDFS), and, in particular, with those …