We propose a high-speed and energy-efficient two-cycle multiply-accumulate (MAC)
architecture that supports two's complement numbers, and includes accumulation guard bits …

The paper presents the implementation of MAC (multiplieraccumulator) unit using Vedic
multiplier. The speed of MAC depends on the speed of the multiplier. The Vedic multiplier …

The design of an embedded processor is dependent on the application domain.
Traditionally, design solutions specific to an application domain have been available in …

This paper proposes a novel fixed point complex number multiply accumulate circuit, which
is used in real time digital signal processing applications. The proposed architecture …

32x32-bit multiply accumulate (MAC) unit designed using ancient Vedic mathematical
techniques. This research work presents the efficiency of Urdhva Triyagbhyam Vedic …

An Efficient MAC Design for Image Processing Application Page 1 Indian Journal of
Science and Technology, Vol 11(19), DOI: 10.17485/ijst/2018/v11i19/123226, May 2018 …

The FlexCore processor is the resulting implementation of an exposed datapath approach
conceptualized in the FlexSoC programme. By way of a crossbar switch interconnect, all …

We propose a low power and area efficient two-cycle multiply-accumulate (2C-MAC)
architecture which supports 2's complement numbers, and includes accumulation guard bits …