Semiconductor package structure and manufacturing method thereof

JY Wu, CH Yu, CS Liu, CH Lee - US Patent 10,461,022, 2019 - Google Patents
(57) ABSTRACT A semiconductor structure includes a first die including a first surface and a
second surface opposite to the first surface; a molding surrounding the first die; a first via …

Molded chip combination

MS Bhagavat, L Fu, I Barber, CK Leong… - US Patent …, 2019 - Google Patents
Various molded chip combinations and methods of manu facturing the same are disclosed.
In one aspect, a molded chip combination is provided that includes a first semicon ductor …

Devices, packaging devices, and methods of packaging semiconductor devices

HW Chen, AJ Su, JM Wang - US Patent 10,177,032, 2019 - Google Patents
Devices, packaging devices, and methods of packaging semiconductor devices are
disclosed. In some embodiments, a packaged semiconductor device includes a molding …

Integrated fan-out packages

S Jeng, C Dai-Jang, HT Lu, HW Liu, CH Lin… - US Patent …, 2019 - Google Patents
Integrated fan-out packages and methods of forming the same are disclosed. An integrated
fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out …

Molded die last chip combination

MS Bhagavat, R Agarwal - US Patent 10,593,628, 2020 - Google Patents
(2013 01); H01 L 21/485 (201301); H0 IL 21/486 (2013 01); H01 L 21/4853 (2013 01); H01L
21/4857 (2013 01); H01L 21/663 (201301); H01 L 23/49822 (2013 01); H0IL 23/49827 …

Fan-out semiconductor package

DH Lee, TJ Cho - US Patent 11,043,441, 2021 - Google Patents
A semiconductor package includes: a semiconductor chip having an active surface, having
connection pads disposed thereon, and an inactive surface, opposing the active surface; an …

High density cross link die with polymer routing layer

CH Lin, R Agarwal, M Bhagavat, F Guo - US Patent 10,923,430, 2021 - Google Patents
Various multi-die arrangements and methods of manufac turing the same are disclosed. In
one aspect, a semiconduc tor chip device is provided that includes a first molding layer and …

Integrated fan-out packages and methods of forming the same

TH Lee, CH Yu, CM Tsai, HJ Kuo, MC Ho - US Patent 10,861,814, 2020 - Google Patents
Integrated fan-out packages and methods of forming the same are disclosed. An integrated
fan-out package includes a bump structure, a polymer layer and a metal layer. The bump …

Microelectronics assembly including top and bottom packages in stacked configuration with shared cooling

R Sankman, MA Hossain, A Nalamalpu… - US Patent …, 2024 - Google Patents
An integrated circuit structure that includes a first integrated circuit package and a second
integrated circuit package is described. The two packages can be stacked above, for …

Semiconductor package and method for manufacturing same

HS Jang, GY Kim - US Patent App. 15/245,306, 2017 - Google Patents
Provided are a semiconductor package and method for manufacturing the same. The
semiconductor package includes a first semiconductor chip. A first mold layer is disposed on …