RTL Design and Logic Synthesis of Traffic Light Controller for 45nm Technology

A Devipriya, H Girish, V Srinivas… - 2022 3rd …, 2022 - ieeexplore.ieee.org
In many cities, traffic regulation is a difficult challenge to solve. This is due to the large
number of cars and the traffic system's high dynamics. Poor traffic network are a major cause …

PAOD: a predictive approach for optimization of design in FinFET/SRAM

H Girish, DR Shashikumar - International Journal of Electrical …, 2019 - search.proquest.com
The evolutions in the modern memory units are comeup with FinFET/SRAM which can be
utilized over high scaled computing units and in other devices. Some of the recent systems …

SECURE SMART DOOR LOCK FEATURING FACIAL RECOGNITION

KR Mamatha, S Thejaswini… - Machine …, 2024 - machineintelligenceresearchs.com
Identity fraud has become a big concern in today's society which increasing number of risks.
A face recognition system must be built to prevent these thefts and identity fraud. For the …

A novel optimization framework for controlling stabilization issue in design principle of FinFET based SRAM

H Girish, DR Shahshikumar - International Journal of Electrical …, 2019 - search.proquest.com
The conventional design principle of the finFET offers various constraints that act as an
impediment towards improving ther performance of finFET SRAM. After reviewing existing …

SOPA: Search Optimization Based Predictive Approach for Design Optimization in FinFET/SRAM

H Girish, DR Shashikumar - … in Intelligent Systems: Proceedings of 7th …, 2019 - Springer
FinFET/SRAM has been contributing to the new evolution of modern-day memory units that
are used over broader scale of computing units and other sophisticated devices. A review …

Enhancing Traffic Efficiency with a Custom Verilog Traffic Light Controller

S Sharma, S Singh - 2024 15th International Conference on …, 2024 - ieeexplore.ieee.org
This paper presents the design and implementation of a traffic light controller system, aimed
at optimizing traffic flow at intersections. The system is developed using Verilog HDL, and it …

Design And Validation Of A 32-Bit RISC-V Processor Incorporating Vedic Mathematics

H Girish, V Shylaja, D Vijayalakshmi… - … : Theory and Practice, 2024 - kuey.net
A Vedic multiplier architecture is employed in constructing a 32-bit RISC-V processor to
enhance speed and reduce computational complexity. It's ALU and MAC units, based on …

[PDF][PDF] Laser Fencing Surveillance System With Email Alert

KR Mamatha - … Administration: Theory and Practice, 30 (2), 2024 - researchgate.net
This work presents an antitheft alert system that integrates multiple technologies to offer a
high level of detection, monitoring, and barrier protection through costeffective methods and …

[PDF][PDF] Performance Evaluation Of AI Models In Early Heart Disease Diagnosis

S Thejaswini - … Administration: Theory and Practice, 30 (2), 2024 - researchgate.net
Machine learning is increasingly being utilized throughout various stages of healthcare,
particularly in predicting conditions like locomotor disorders and heart disease. Treating …

[PDF][PDF] Collision Alert System for Vehicles Using GSM Technology

SK Suhas, H Girish, MK Revathi, MK Gayathiri - researchgate.net
Road accidents represent a grave global concern, causing tragic fatalities worldwide. India
currently tops the list of nations grappling with this issue, necessitating immediate attention …