A tutorial on multiplierless design of FIR filters: Algorithms and architectures
Finite impulse response (FIR) filtering is a ubiquitous operation in digital signal processing
systems and is generally implemented in full custom circuits due to high-speed and low …
systems and is generally implemented in full custom circuits due to high-speed and low …
An algorithm for the design of low-power hardware-efficient FIR filters
<? Pub Dtl=""?> A novel algorithm for designing low-power and hardware-efficient linear-
phase finite-impulse response (FIR) filters is presented. The algorithm finds filter coefficients …
phase finite-impulse response (FIR) filters is presented. The algorithm finds filter coefficients …
Table-based versus shift-and-add constant multipliers for FPGAs
The multiplication by a constant is a frequently used operation. To implement it on Field
Programmable Gate Arrays (FPGAs), the state of the art offers two completely different …
Programmable Gate Arrays (FPGAs), the state of the art offers two completely different …
Truncated multiple constant multiplication with minimal number of full adders
Many algorithms from digital signal processing, including digital filters or discrete transforms,
require the multiplications with several constants. These can be efficiently implemented …
require the multiplications with several constants. These can be efficiently implemented …
[图书][B] Multiple constant multiplication optimizations for field programmable gate arrays
M Kumm, P Zipf - 2016 - Springer
As silicon technology advances, field programmable gate arrays appear to gain ground
against the traditional ASIC project starts, reaching out to form the mainstream …
against the traditional ASIC project starts, reaching out to form the mainstream …
Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications
In this paper, critical path of multiple constant multiplication (MCM) block is analyzed
precisely and optimized for high-speed and low-complexity implementation. A delay model …
precisely and optimized for high-speed and low-complexity implementation. A delay model …
High-level synthesis algorithm for the design of reconfigurable constant multiplier
J Chen, CH Chang - … transactions on computer-aided design of …, 2009 - ieeexplore.ieee.org
Multiplying a signal by a known constant is an essential operation in digital signal
processing algorithms. In many application scenarios, an input or output signal is repeatedly …
processing algorithms. In many application scenarios, an input or output signal is repeatedly …
Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability
Multiplierless constant multiplication using bit-shifts, additions and subtractions has been an
active research topic in the last decades. The multiplication with multiple constants, known …
active research topic in the last decades. The multiplication with multiple constants, known …
Design of optimal multiplierless FIR filters with minimal number of adders
This work presents two novel methods that simultaneously optimize both the design of a
finite impulse response (FIR) filter and its multiplierless hardware implementation. We use …
finite impulse response (FIR) filter and its multiplierless hardware implementation. We use …
Design of high‐speed, low‐power, and area‐efficient FIR filters
In a recent work, we have introduced a new multiple constant multiplication (MCM)
algorithm, denoted as RADIX‐2r. The latter exhibits the best results in speed and power …
algorithm, denoted as RADIX‐2r. The latter exhibits the best results in speed and power …