Dynamic partial self-reconfiguration: Quick modeling, simulation, and synthesis

A Schallenberg - 2010 - oops.uni-oldenburg.de
In dieser Arbeit wird mit OSSS+ R ein Ansatz zur Vereinfachung des Entwurfs dynamisch
partiell rekonfigurierbarer Systeme mit FPGAs vorgesellt. Die Modellierung erfolgt …

Technical debt management in the brazilian federal administration

TR De Assuncao, I Rodrigues, E Venson… - 2015 6th Brazilian …, 2015 - ieeexplore.ieee.org
Technical Debt (TD) is a metaphor to refer to events that bring quality loss in the code. A
large volume of Technical Debt in an application may bring losses for the organisation that …

System-level modeling of a Reconfigurable System on Chip for wireless sensor networks applications

GS Beserra, JEG de Medeiros… - … on Intelligent and …, 2010 - ieeexplore.ieee.org
This paper presents the system-level modeling of a Reconfigurable System on Chip (RSoC)
that is being currently developed in our institution. Although there is a wide range of possible …

A reconfigurable processor architecture combining multi-core and reconfigurable processing units

L Yan, B Wu, Y Wen, S Zhang, T Chen - Telecommunication Systems, 2014 - Springer
It'sa promising way to improve performance significantly by adding reconfigurable
processing unit (RPU) to a general purpose processor. In this paper, a Reconfigurable Multi …

Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture

MM Pereira, SRF de Araújo, BC de Gliveira… - Proceedings of the 2008 …, 2008 - dl.acm.org
This paper presents a strategy to modify a sequential implementation of an H. 264/AVC
motion estimation to run on a new reconfigurable architecture called RoSA. The …

Modelagem em nível transacional de sistemas em chip mistos para aplicações de redes de sensores sem fio

GS Beserra - 2011 - realp.unb.br
Este trabalho apresenta a modelagem em nível de sistema de SoCs mistos que estão
sendo desenvolvidos nesta instituição, voltados inicialmente para aplicações envolvendo …

SAT: A Stream Architecture Template for Embedded Applications

Q Yang, N Wu, M Wen, Y He, H Su… - 2010 10th IEEE …, 2010 - ieeexplore.ieee.org
The increase of embedded applications complexity has demanded hardware more flexible
while providing higher performance. Reconfigurable architectures and stream processing …

Brick: a multi-context expression grained reconfigurable architecture

JF Eusse, M Hübner, RP Jacobi - … of the 22nd Annual Symposium on …, 2009 - dl.acm.org
In this work, we explore a new family of coarse grain reconfigurable architecture called
BRICK, which is capable of mapping complete expressions and pipelines into one …

Signal Processing Domain Application Mapping on the Brick Reconfigurable Array

JFE Giraldo, RP Jacobi - 2009 International Conference on …, 2009 - ieeexplore.ieee.org
This paper introduces the proposal of an expression grain reconfigurable architecture called
BRICK, its functionality and main components. A mapping for three signal processing …

[PDF][PDF] Estudo sobre o Impacto do Processador Hospedeiro no Desempenho das Arquiteturas Reconfiguráveis Híbridas

ASB Lopes, MB da Costa, MM Pereira, IS Silva¹ - sbc.org.br
Esse artigo apresenta um estudo que relaciona a escolha do processador hospedeiro com
o desempenho das arquiteturas reconfiguráveis híbridas. Como estudo de caso foram …