Technology and device scaling considerations for CMOS imagers
HS Wong - IEEE Transactions on electron Devices, 1996 - ieeexplore.ieee.org
This paper presents an analysis of the impact of device and technology scaling on active
pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device …
pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device …
CMOS imager with storage capacitor
HE Rhodes - US Patent 6,204,524, 2001 - Google Patents
E. 6. E. Ebel A CMOS imager having an improved signal to noise ratio 5.47, 515 11 f1995
Fossum et al. and improved dynamic range is disclosed. The CMOS 5506.429 4/1996 …
Fossum et al. and improved dynamic range is disclosed. The CMOS 5506.429 4/1996 …
CMOS imager with selectively silicided gates
HE Rhodes - US Patent 6,333,205, 2001 - Google Patents
The invention also relates to an apparatus and method for selectively providing a silicide
coating over the transistor gates of a CMOS imager to improve the speed of the transistor …
coating over the transistor gates of a CMOS imager to improve the speed of the transistor …
Retrograde well structure for a CMOS imager
HE Rhodes, M Durcan - US Patent 6,310,366, 2001 - Google Patents
(57) ABSTRACT A retrograde well structure for a CMOS imager that improves the quantum
efficiency and Signal-to-noise ratio of the imager. The retrograde well comprises a doped …
efficiency and Signal-to-noise ratio of the imager. The retrograde well comprises a doped …
Vcc pump for CMOS imagers
HE Rhodes - US Patent 6,140,630, 2000 - Google Patents
5,323,052 6/1994 Koyama.................................. 257/294 57 ABSTRACT 5,324,958 6/1994
Mead et al.............................. 257/291 5,461,425 10/1995 Fowler et al.. A CMOS imaging …
Mead et al.............................. 257/291 5,461,425 10/1995 Fowler et al.. A CMOS imaging …
CMOS imager with a self-aligned buried contact
HE Rhodes - US Patent 6,326,652, 2001 - Google Patents
An imaging device formed as a CMOS Semiconductor integrated circuit includes a buried
contact line between the floating diffusion region and the gate of a Source follower output …
contact line between the floating diffusion region and the gate of a Source follower output …
Multi-layered gate for a CMOS imager
HE Rhodes - US Patent 6,376,868, 2002 - Google Patents
5,471.515 A 11/1995 Fossum et al. formed adjacent to it which has a Second conductive
layer 5,506.429 A 4/1996 Tanaka et al. that extends at least partially over the Surface of the …
layer 5,506.429 A 4/1996 Tanaka et al. that extends at least partially over the Surface of the …
Retinomorphic vision systems
K Boahen - Proceedings of Fifth International Conference on …, 1996 - ieeexplore.ieee.org
The new generation of silicon retinae has two defining characteristics. First, these synthetic
retinae are morphologically equivalent to their biological counterparts-at an appropriate …
retinae are morphologically equivalent to their biological counterparts-at an appropriate …
A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications
TS Jung, YJ Choi, KD Suh, BH Suh… - … Solid-State Circuits …, 1996 - ieeexplore.ieee.org
The NAND flash memory was originally designed to target solid-state mass storage
applications. Key requirements of mass storage, low cost and high serial access throughput …
applications. Key requirements of mass storage, low cost and high serial access throughput …
Single chip camera device having double sampling operation
ER Fossum, R Nixon - US Patent 6,456,326, 2002 - Google Patents
(57) ABSTRACT A Single chip camera device is formed on a single Substrate including an
image acquisition portion for control portion and the timing circuit formed on the Substrate …
image acquisition portion for control portion and the timing circuit formed on the Substrate …