A modified macro model approach for SPICE based simulation of single electron transistor
A new macro model of single electron transistor (SET) for SPICE based simulation of SET
circuits is proposed. Two voltage controlled current sources and some scaling factors are …
circuits is proposed. Two voltage controlled current sources and some scaling factors are …
A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits
To explore single-electron circuits for different applications, a proper simulation platform
where circuits consisting of single electron transistors and other devices can be simulated …
where circuits consisting of single electron transistors and other devices can be simulated …
A new static differential design style for hybrid SET–CMOS logic circuits
MM Abutaleb - Journal of Computational Electronics, 2015 - Springer
Single electron transistors (SETs) have ultra-small size, ultra-low power dissipation and
unique Coulomb blockade oscillation characteristics which make them promising …
unique Coulomb blockade oscillation characteristics which make them promising …
Width minimization in the single-electron transistor array synthesis
CW Liu, CE Chiang, CY Huang… - … , Automation & Test …, 2014 - ieeexplore.ieee.org
Power consumption has become one of the primary challenges to meet the Moore's law. For
reducing power consumption, Single-Electron Transistor (SET) at room temperature has …
reducing power consumption, Single-Electron Transistor (SET) at room temperature has …
A reconfigurable low-power BDD logic architecture using ferroelectric single-electron transistors
This paper presents ferroelectric single-electron transistors (SETs) with tunable tunnel
barriers and their application in a reconfigurable binary decision diagram (BDD) logic …
barriers and their application in a reconfigurable binary decision diagram (BDD) logic …
A defect-aware approach for mapping reconfigurable single-electron transistor arrays
Single-Electron Transistor (SET) at room temperature has been demonstrated as a
promising device for extending Moore's law due to its ultra low power consumption …
promising device for extending Moore's law due to its ultra low power consumption …
Synthesis for width minimization in the single-electron transistor array
CW Liu, CE Chiang, CY Huang… - … Transactions on Very …, 2015 - ieeexplore.ieee.org
Power consumption has become one of the primary challenges to meetMoore's law. For
reducing power consumption, single-electron transistor (SET) at room temperature has been …
reducing power consumption, single-electron transistor (SET) at room temperature has been …
Area-aware decomposition for single-electron transistor arrays
Single-electron transistor (SET) at room temperature has been demonstrated as a promising
device for extending Moore's law due to its ultra-low power consumption. Existing SET …
device for extending Moore's law due to its ultra-low power consumption. Existing SET …
Formal verification with EDA application and hardware prototyping platform
TP Leao, PDF de Medeiros Félix… - US Patent …, 2021 - Google Patents
A formal verification EDA application can be configured to receive a circuit design of an IC
chip. The circuit design of the IC chip comprises a set of properties for the IC chip and …
chip. The circuit design of the IC chip comprises a set of properties for the IC chip and …
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays
CC Wu, KH Ho, JD Huang… - 2018 IEEE Computer …, 2018 - ieeexplore.ieee.org
Power consumption has become a primary obstacle for circuit designs at present. Single-
Electron Transistor (SET) at room temperature has been demonstrated as a promising …
Electron Transistor (SET) at room temperature has been demonstrated as a promising …