The continuing increase in functional requirements of modern hardware designs means the
traditional functional verification process becomes inefficient in meeting the time-to-market …

With the ever-increasing hardware design complexity comes the realization that efforts
required for hardware verification increase at an even faster rate. Driven by the push from …

This paper introduces a new methodology for digital design properties extraction from
simulation traces. The innovated methodology is based on a new data mining technique …

Mining from simulation data of the golden model in hardware design verification is an
effective solution to assertion generation. While the simulation data is inherently incomplete …

This paper introduces a new methodology for digital design properties extraction from
simulation traces. A new Breadth-First Decision Tree (BF-DT) mining algorithm is proposed …

Mining from simulation data has been introduced as an effective solution to assertion
generation for the design under verification (DUV) in prior work. As the simulation data is …

GoldMine automatically generates assertions for register transfer level (RTL) designs using
a combination of static analysis and machine learning algorithms. We compare four different …

The rapid pace of technology nowadays is causing more and more hardware complexity.
Functional Verification is a major part of the process of Digital Integrated Circuits Design …

Digital systems, such as an Internet-of-Things (IoT) device, are becoming ubiquitous. An IoT
device integrator may rely on third-party vendors for Microprocessor cores which may …

Modern digital chip designers face increased security challenges when using third-party
intellectual property (3PIP) in their designs. Using formal verification techniques …