Composition analysis of the surface of silicon nitride before exposure to the R0460881bleu,
2ed 63green anhydrous HF & solvent (or alcohol) additive release process, No oxygen …

Forming a first sidewall spacer adjacent a vertically oriented channel semiconductor
structure (“VCS structure') and adjacent a cap layer, performing at least one planarization …

One illustrative method disclosed herein includes, among other things, forming an initial
vertically oriented channel semiconductor structure having a first height above a Sub strate …

US9799751B1 - Methods of forming a gate structure on a vertical transistor device - Google
Patents US9799751B1 - Methods of forming a gate structure on a vertical transistor device …

(57) ABSTRACT A method of manufacturing a semiconductor device includes forming a
mask layer on a semiconductor substrate, etching the semiconductor Substrate using the …

Field effect transistors and methods of forming the same include forming a stack of
nanosheets of alternating layers of channel material and sacrificial material. A layer of …

Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A
source and drain region is positioned at respective ends of the vertically arranged channel …

The present invention provides techniques for integrating a III-V, SiGe, or Ge fin base bipolar
transistor with CMOS finFET technology. In one aspect of the invention, a method of …

One illustrative method disclosed herein includes, among other things, forming first and
second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and …

One illustrative method disclosed herein includes, among other things, forming an initial
bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel …