Emerging memory technologies: Trends, challenges, and modeling methods
In this paper we analyze the possibility of creating a universal non-volatile memory in a near
future. Unlike DRAM and flash memories a new universal memory should not require …
future. Unlike DRAM and flash memories a new universal memory should not require …
Method of constructing a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond
T Hamamoto, T Ohsawa - Solid-State Electronics, 2009 - Elsevier
Floating body cell (FBC) is a one-transistor memory cell on SOI substrate aimed at high-
density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb …
density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb …
The new era of scaling in an SoC world
M Bohr - 2009 IEEE International Solid-State Circuits …, 2009 - ieeexplore.ieee.org
The time has passed when traditional MOSFET scaling techniques were adequate to meet
the needs of microprocessor products, but that has not meant the end of Moore's Law nor the …
the needs of microprocessor products, but that has not meant the end of Moore's Law nor the …
Vertical floating body cell of a semiconductor device and method for fabricating the same
SW Chung - US Patent 7,663,188, 2010 - Google Patents
(57) ABSTRACT A semiconductor device includes a tube-type channel formed over a
semiconductor Substrate. The tube-type channel is connected to first and second conductive …
semiconductor Substrate. The tube-type channel is connected to first and second conductive …
Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Method of forming three dimensional integrated circuit devices using layer transfer technique
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
US8362482B2 - Semiconductor device and structure - Google Patents US8362482B2 -
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Method for fabrication of a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist - US Patent 8,557,632, 2013 - Google Patents
US8557632B1 - Method for fabrication of a semiconductor device and structure - Google
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …