Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques

A Vijayakumar, VC Patil, DE Holcomb… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
The threat of hardware reverse engineering is a growing concern for a large number of
applications. A main defense strategy against reverse engineering is hardware obfuscation …

Opportunities for machine learning in electronic design automation

PA Beerel, M Pedram - 2018 IEEE International Symposium on …, 2018 - ieeexplore.ieee.org
The rise of machine learning (ML) has introduced many opportunities for computer-aided-
design, VLSI design, and their intersection. Related to computer-aided design, we review …

Multi-bit pulsed-latch based low power synchronous circuit design

K Singh, OAR Rosas, H Jiao, J Huisken… - … on Circuits and …, 2018 - ieeexplore.ieee.org
Pulsed-latches emerge as an ideal sequencing element for low power digital circuit design,
serving as an alternative of flip-flops. In this paper, low power multi-bit pulsed-latches are …

In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations

W Jin, S Kim, W He, Z Mao… - IEEE Transactions on Very …, 2016 - ieeexplore.ieee.org
In order to achieve high tolerance against process, voltage, and temperature variations in
the ultralow voltage (ULV) circuits, in situ error detection and correction (EDAC) techniques …

A wide-voltage-range transition-detector with in-situ timing-error detection and correction based on pulsed-latch design in 28 nm CMOS

X Shang, M Lu, C Wu, Y Xiang, J Xu… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Excessive timing margins are usually added in the wide-voltage-range design due to
process, voltage and temperature (PVT) variations, which can be eliminated by adaptive …

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

F Minnella, J Cortadella, MR Casu, MT Lazarescu… - IEEE …, 2023 - ieeexplore.ieee.org
Flip-flops are the most used sequential elements in synchronous circuits, but designs based
on latches can operate at higher frequencies and occupy less area. Techniques to increase …

Near- and Sub- Pipelines Based on Wide-Pulsed-Latch Design Techniques

W Jin, S Kim, W He, Z Mao… - IEEE Journal of Solid-State …, 2017 - ieeexplore.ieee.org
This paper presents a methodology and chip demonstration to design near-/sub-threshold
voltage (Vt) pipelines using pulsed latches that are clocked at very wide pulses. Pulsed-latch …

Reliability enhancement of low-power sequential circuits using reconfigurable pulsed latches

WM Elsharkasy, A Khajeh, AM Eltawil… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an
alternative sequential element with high performance and low area and power consumption …

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

S Paik, GJ Nam, Y Shin - 2011 IEEE/ACM International …, 2011 - ieeexplore.ieee.org
A pulsed-latch can be modeled as a fast flip-flop. This allows conventional flip-flop designs
to be migrated to pulsed-latch versions by simple replacement to reduce the clocking power …

Converting flip-flop to clock-gated 3-phase latch-based designs using graph-based retiming

H Cheng, X Li, Y Gu, PA Beerel - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Latches have the advantages of timing-borrowing, smaller cell area, lower input
capacitance, and lower power compared to flip-flops (FFs). This article presents a CAD flow …