Data output circuit, memory device including the data output circuit, and operating method of the memory device
P Hyunsoo, Y Kim, C Lee - US Patent 10,559,334, 2020 - Google Patents
(57) ABSTRACT A memory device includes a memory cell array storing input data, a clock
generator circuit generating first clocks and second clocks using a reference clock, a phase …
generator circuit generating first clocks and second clocks using a reference clock, a phase …
Semiconductor device for generating initialization of information in response to a first clock and outputting the initialization information in response to a second clock
M Jinyeong - US Patent 9,324,385, 2016 - Google Patents
An embodiment of the present invention is directed to a semiconductor device that Supports
a burst ordering opera tion. In accordance with an embodiment of the present inven tion, a …
a burst ordering opera tion. In accordance with an embodiment of the present inven tion, a …
Memory device with flexible data pin configuration and method thereof
M Yoon - US Patent 12,079,492, 2024 - Google Patents
A memory device includes at least one memory bank, a plurality of data pins coupled to a
plurality of package pins, a data input/output (IO) circuit, at least one bank IO circuit and a …
plurality of package pins, a data input/output (IO) circuit, at least one bank IO circuit and a …
Semiconductor memory device
YM Kim - US Patent 8,780,646, 2014 - Google Patents
GIICS/00(2006.01) A semiconductor memory device includes a pipe latch circuit GIIC
8/18(2006.01) configured to receive parallel input data and output serial data (52) US Cl. or …
8/18(2006.01) configured to receive parallel input data and output serial data (52) US Cl. or …
Semiconductor device
HG Kim, DH Ra, BK Yoon, MS Han - US Patent 10,762,933, 2020 - Google Patents
A semiconductor device includes a latch control circuit configured to generate a latch input
signal, which is enabled in response to a latency signal, and configured to generate a latch …
signal, which is enabled in response to a latency signal, and configured to generate a latch …
Semiconductor memory device and semiconductor system having the same
KC Chun - US Patent 9,672,896, 2017 - Google Patents
(57) ABSTRACT A semiconductor memory device may include: a data align ment signal
generation unit Suitable for generating an align ment signal corresponding to an input …
generation unit Suitable for generating an align ment signal corresponding to an input …
Output circuit for implementing high speed data transmition
An output circuit includes first and second output drivers. The first output driver is configured
to transfer a first data signal directly to an output pad in synchronization with a clock signal …
to transfer a first data signal directly to an output pad in synchronization with a clock signal …