Major operation block in any processing unit is a multiplier. There are many multiplication
algorithms are proposed, by using which multiplier structure can be designed. Among …

The primitive constraints in any VLSI system design are power, delay and area. Systems
based on CMOS logic consume more power and area. Higher power dissipation will have a …

Practical implementation of deep neural networks (DNNs) demands significant hardware
resources, necessitating high computational power and memory bandwidth. While existing …

As the digital electronic systems are getting better with the advancement in technology day
by day; there is a need to build faster and more power-efficient multipliers, which are the …

The efficient and precise hardware implementations of tanh and sigmoid functions play an
important role in various neural network algorithms. Different applications have different …

Contemporary hardware implementations of deep neural networks face the burden of
excess area requirement due to resource-intensive elements such as a multiplier. A semi …

In the work below we have formulated and examined 8-bit vedic multiplier using (RC) Ripple
carry adder,(CSL) Carry select adder,(CSl) Carry select adder using Binary to excess-1 …

This research work proposes the vedic multiplier architecture with different carry lookahead
adders like regular carry lookahead adder (RCLA), block carry lookahead adder (BCLA) …

In order to improve the performance of deep neural network (DNN) accelerators, it is
necessary to optimize compute efficiency and operating frequency. However, the …

At the end of all fixed point multiplications is one last long addition that needs to be
performed. In this paper, we show how the choice of this last adder has significant effect on …