Leakage reduction in 18 nm FinFET based 7T SRAM cell using self controllable voltage level technique

TS Kumar, SL Tripathi - Wireless Personal Communications, 2021 - Springer
As the technology is scaled the power consumption increases significantly, because of
which the battery life of portable devices is reduced. Due to high power density, the …

Process evaluation in FinFET based 7T SRAM cell

TS Kumar, SL Tripathi - Analog Integrated Circuits and Signal Processing, 2021 - Springer
The main aim of device scaling or usage of different technology is to reduce power. The
major problem with technology scaling is power dissipation and stability of the device …

Comparative analysis of leakage power in 18nm 7T and 8T SRAM cell Implemented with SVL Technique

TS Kumar, SL Tripathi, SK Sinha - … International Conference on …, 2020 - ieeexplore.ieee.org
The major constraint in present days in system design is power dissipation, there are two
types of power dissipation Dynamic and static power. In the present day level of technology …

A 4× 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications

C Duari, S Birla, AK Singh - Semiconductor Science and …, 2021 - iopscience.iop.org
In ultra-low-power applications, the design of power-efficient static random access memory
(SRAM) is a major concern as it plays a significant part in leakage due to its higher density …

Design of 7T SRAM Cell Using FinFET Technology

TS Kumar, SL Tripathi - Advanced VLSI Design and Testability …, 2020 - taylorfrancis.com
In the current chip technology, the capability of silicon-on-chip (SOC) memory is quickly
developing to increment worldwide execution. As a more prominent reserve memory is …