Configuring floating point operations in a programmable logic device
M Langhammer - US Patent 7,865,541, 2011 - Google Patents
A programmable logic device is programmed to perform arithmetic operations in an internal
format that, unlike known standard formats that store numbers in normalized form and …
format that, unlike known standard formats that store numbers in normalized form and …
Specialized processing block for programmable logic device
KYM Lee, M Langhammer, YW Lin… - US Patent …, 2012 - Google Patents
A specialized processing block for a programmable logic device includes circuitry for
performing multiplications and sums thereof, as well as circuitry for rounding the result. The …
performing multiplications and sums thereof, as well as circuitry for rounding the result. The …
Specialized processing block for programmable logic device
M Langhammer, KYM Lee, O Azgomi… - US Patent …, 2012 - Google Patents
(57) ABSTRACT A specialized processing block for a programmable logic device
incorporates a fundamental processing unit that per forms a sum of two multiplications …
incorporates a fundamental processing unit that per forms a sum of two multiplications …
Large multiplier for programmable logic device
M Langhammer, K Tharmalingam - US Patent 7,930,336, 2011 - Google Patents
4.215. 406 A 7, 1980 Gomola et al. before adding. In one embodiment, this allows all but the
final 42 15.407 A 7, 1980 Gomola et al. addition to take place in specialized processing …
final 42 15.407 A 7, 1980 Gomola et al. addition to take place in specialized processing …
Multiple-precision processing block in a programmable integrated circuit device
M Langhammer - US Patent 9,189,200, 2015 - Google Patents
A specialized processing block in a programmable integrated circuit device is configurable
to perform floating-point arithmetic operations at selectable different precisions. The …
to perform floating-point arithmetic operations at selectable different precisions. The …
Large multiplier for programmable logic device
M Langhammer, K Tharmalingam - US Patent 8,788,562, 2014 - Google Patents
A plurality of specialized processing blocks in a programmable logic device, including
multipliers and circuitry for adding results of those multipliers, can be configured as a larger …
multipliers and circuitry for adding results of those multipliers, can be configured as a larger …
Specialized processing block with fixed-and floating-point structures
M Langhammer - US Patent 9,098,332, 2015 - Google Patents
(56) References Cited 5,636,150 A 6/1997 Okamoto 5,636,368 A 6/1997 Harrison et al. US
PATENT DOCUMENTS 5,640,578 A 6/1997 Balmer et al. 5,644,519 A 7, 1997 Yatim et al …
PATENT DOCUMENTS 5,640,578 A 6/1997 Balmer et al. 5,644,519 A 7, 1997 Yatim et al …
Combined interpolation and decimation filter for programmable logic device
V Mauer - US Patent 7,814,137, 2010 - Google Patents
A programmable logic device can be configured as a finite impulse response (FIR) filter
capable of operating in either interpolation mode or decimation mode and of switching …
capable of operating in either interpolation mode or decimation mode and of switching …
Multiplier-accumulator circuitry and methods
KH Choe, TK Ngai, HY Lui - US Patent 8,645,450, 2014 - Google Patents
Multiplier-accumulator circuitry includes circuitry for form ing a plurality of partial products of
multiplier and multipli candinputs, carry-save adder circuitry for adding together the partial …
multiplier and multipli candinputs, carry-save adder circuitry for adding together the partial …
Specialized processing block for programmable logic device
KYM Lee, M Langhammer, TM Nguyen… - US Patent …, 2012 - Google Patents
A specialized processing block for a programmable logic device includes circuitry for
performing multiplications and sums thereof, as well as circuitry for performing floating point …
performing multiplications and sums thereof, as well as circuitry for performing floating point …