This paper presents an algorithm to statically schedule live and strongly connected Marked
Graphs. The proposed algorithm computes the best execution where the execution rate is …

We have defined a full design flow starting from high-level domain specific languages
(Simulink, SCADE, AADL, SysML, MARTE, SystemC) and going all the way to the …

In recent years, minimizing the power consumption has become a key issue in the design of
portable electronic devices. In this paper, low power architecture which can support the real …

Abstract Originally the Latency Insensitive Protocols (LIP) were invented to make a system
elastic to the interconnect latencies using handshaking signals such as 'valid'and 'stall' …

Synchronous models are used to specify embedded systems functions in a clear and
unambiguous way and allow verification of properties using formal methods. The …

Process Networks have long been used as formal Models of Computation in the design of
dedicated hardware and software embedded systems and Systems-on-Chip. Choice-less …

Timing Closure in presence of long global wire interconnects is one of the main current
issues in System-on-Chip design. One proposed solution to the Timing Closure problem is …

The advent of chip-level parallel architectures prompted a renewal of interest into dataflow
process networks. The trend is to model an application independently from the architecture …

Cette thèse présente de nouveaux résultats liant la théorie des systèmes dits insensibles à
la latence, à une sous-classe des réseaux de Pétri dénommée Marked Event Graph et son …

Cette thèse définit un nouveau modèle de calcul et de communication, dénommé graphe à
routage k-périodique (KRG). Ce modèle, de la famille des réseaux de processus flots de …