Machine learning-assisted global optimization methods for speeding up analog integrated
circuit sizing is attracting much attention. However, often a few typical analog integrated …

In this paper, the idea of electrically doped (ED) Nano-scale TFETs is used to design a non-
tunneling n-type NWFET with an additional gate named the side-gate (SG). The work …

This work presented a comparison between two Voltage Controlled Oscillators (VCOs)
designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) …

In this paper, we present a fully integrated circuit without inductance implementing Chua's
chaotic system. The circuit described in this study utilizes the SMIC 180 nm CMOS process …

A symbolic expression that approximates the output frequency of the submicron differential
ring oscillator, using the detailed transient behavior of the MOSFETs, is presented in this …

The optimization of analog integrated circuits requires to take into account a number of
considerations and trade-offs that are specific to each circuit, meaning that each case of …

An on-chip nanopower RC relaxation oscillator is developed in a 180-nm standard CMOS
process, consuming 300 nW while running at 10 kHz. Employing a frequency compensation …

Real applications of integrated circuits (ICs) require satisfying strong target specifications,
which challenge is focused on trading off specifications that are in conflict, ie improving one …

This research paper proposes the design of an active-loaded differential amplifier using the
Double-Gate (DG) MOSFET. This differential amplifier employs feedback and simplifies a …

In this article, a variation-aware design methodology for high-performance MOS-varactor
voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is …