Ant colony algorithms analogize the social behaviour of ant colonies, they are a class of
meta-heuristics which are inspired from the behavior of real ants. It was applied successfully …

The article examines the market and technology trends affecting the testing of integrated
circuits, with emphasis on the role of predesigned components-cores-and built in self test …

This paper proposes a behavioral-level test pattern generation algorithm for behavioral
VHDL descriptions. The proposed approach is based on the comparison between the …

In this paper, we present an algorithm for generating test patterns automatically from
functional register-transfer level (RTL) circuits that target detection of stuck-at faults in the …

Testing a processor in native mode by executing instructions from cache has been shown to
be very effective in discovering defective chips. In previous work, we showed an efficient …

In recent years, there has been growing interest in behavioral (high-level) synthesis for
testability. This is due to the fact that testability features, such as scan or the built-in self-test …

Executing instructions from the cache has been shown to improve the defect coverage of
real chips. However, although the faults detected by such tests can be determined, there has …

A review is presented of electrical testing, failure mechanisms, fault models, fault simulation,
testability analysis, and test-generation methods for CMOS VLSI circuits. The relationships …

In this paper, we present a technique for extracting functional (control/data flow) information
from register-transfer level controller/data path circuits, and illustrate its use in design for …

Hierarchically designed microprocessor-like VLSI circuits have complex data paths and
embedded control machines to execute instructions. When a test pattern has to be applied to …