Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof

M Tsutsumi, K Kajiwara, RS Makala - US Patent 9,991,277, 2018 - Google Patents
A memory opening can be formed through an alternating stack of insulating layers and
sacrificial material layers over a substrate. A material layer stack containing, from outside to …

Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors

K Miyata, Z Lu, A Lin, D Mao, J Yu, J Alsmeier… - US Patent …, 2016 - Google Patents
2016-01-13 Assigned to SANDISK TECHNOLOGIES INC. reassignment SANDISK
TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

Method of making a vertical NAND device using sequential etching of multilayer stacks

RS Makala, YS Lee, J Pachamuthu, J Alsmeier… - US Patent …, 2015 - Google Patents
2013-07-02 Assigned to SanDisk Technologies, Inc. reassignment SanDisk Technologies,
Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS) …

Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof

A Nishida - US Patent 10,283,493, 2019 - Google Patents
A first die includes a three-dimensional memory device and first copper pads. A second die
includes a peripheral logic circuitry containing CMOS devices located on the semiconductor …

Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof

KH Kim, M Higashitani, F Toyama… - US Patent 10,510,738, 2019 - Google Patents
2019-01-15 Assigned to SANDISK TECHNOLOGIES LLC reassignment SANDISK
TECHNOLOGIES LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …

Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device

P Rabkin, J Pachamuthu, J Alsmeier - US Patent 9,230,980, 2016 - Google Patents
A memory film layer is formed in a memory opening through an alternating stack of first
material layers and second material layers. A sacrificial material layer is deposited on the …

Compact three dimensional vertical NAND and method of making thereof

J Alsmeier, RS Makala, X Costa, Y Zhang - US Patent 8,878,278, 2014 - Google Patents
A NAND device has at least a 3× 3 array of vertical NAND strings in which the control gate
electrodes are continuous in the array and do not have an air gap or a dielectric filled trench …

Multilevel memory stack structure and methods of manufacturing the same

J Pachamuthu, J Alsmeier, H Chien - US Patent 9,230,987, 2016 - Google Patents
US9230987B2 - Multilevel memory stack structure and methods of manufacturing the same
- Google Patents US9230987B2 - Multilevel memory stack structure and methods of …

Cell pillar structures and integrated flows

FA Simsek-Ege, KK Parat - US Patent 9,276,011, 2016 - Google Patents
BACKGROUND Computers and other electronic systems, for example, digi tal televisions,
digital cameras, and cellular phones, often have one or more memory and other devices to …

Methods of fabricating a three-dimensional non-volatile memory device

J Pachamuthu, J Alsmeier, RS Makala… - US Patent 9,230,973, 2016 - Google Patents
(57) ABSTRACT A method of fabricating a semiconductor device, such as a three-
dimensional NAND memory string, includes forming a first stack of alternating layers of a first …