With the rapid developments in very large-scale integration (VLSI) technology, design and
computer-aided design (CAD) techniques, at both the chip and package level, the operating …

This paper reviews the status of present day on-chip wiring design methodologies and
understanding. A brief explanation is given of the fundamental transmission-line properties …

The various arguments for introducing optical interconnections to silicon CMOS chips are
summarized, and the challenges for optical, optoelectronic, and integration technologies are …

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

RLC model creates errors of up to 30% in the total propagation delay of a repeater system.
Considering inductance in repeater insertion is also shown to significantly save repeater …

The authors propose models for both temporal and spatial locality of reference in streams of
requests arriving at Web servers. They show that simple models based on document …

The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as
interconnects for VLSI circuits, while taking into account the practical limitations in this …

Closed form solutions for the 50% delay, rise time, overshoots, and settling time of signals in
an RLC tree are presented. These solutions have the same accuracy characteristics as the …

A global clock distribution strategy used on several microprocessor chips is described. The
clock network consists of buffered tunable trees or treelike networks, with the final level of …

Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …