[图书][B] Fundamentals of tunnel field-effect transistors

S Saurabh, MJ Kumar - 2016 - taylorfrancis.com
During the last decade, there has been a great deal of interest in TFETs. To the best authors'
knowledge, no book on TFETs currently exists. The proposed book provides readers with …

Carrier-transport-enhanced channel CMOS for improved power consumption and performance

S Takagi, T Iisawa, T Tezuka, T Numata… - IEEE transactions on …, 2007 - ieeexplore.ieee.org
An effective way to reduce supply voltage and resulting power consumption without losing
the circuit performance of CMOS is to use CMOS structures using high carrier …

Estimation and compensation of process-induced variations in nanoscale tunnel field-effect transistors for improved reliability

S Saurabh, MJ Kumar - IEEE Transactions on Device and …, 2010 - ieeexplore.ieee.org
Tunnel field-effect transistors (TFETs) have extremely low leakage current, exhibit excellent
subthreshold swing, and are less susceptible to short-channel effects. However, TFETs do …

[图书][B] Strained-Si heterostructure field effect devices

CK Maiti, S Chattopadhyay, LK Bera - 2007 - taylorfrancis.com
A combination of the materials science, manufacturing processes, and pioneering research
and developments of SiGe and strained-Si have offered an unprecedented high level of …

Gallium-nitride-based module with enhanced electrical performance and process for making the same

JC Costa, M Carroll - US Patent 12,027,593, 2024 - Google Patents
The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a
module substrate, a thinned switch die residing over the module substrate, a first mold …

A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

MJ Kumar, V Venkataraman… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
For the first time, a simple and accurate analytical model for the threshold voltage of
nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed …

Wafer-level package with enhanced performance and manufacturing method thereof

JC Costa, J Chadwick, D Jandzinski… - US Patent …, 2021 - Google Patents
The present disclosure relates to a wafer-level package that includes a first thinned die
having a first device layer, a multilayer redistribution structure, a first mold compound, and a …

Wafer-level fan-out package with enhanced performance

JH Hammond, JC Costa, J Chadwick - US Patent 11,069,590, 2021 - Google Patents
The present disclosure relates to a wafer-level fan-out package that includes a first thinned
die, a second die, a multilayer redistribution structure underneath the first thinned die and …

RF devices with enhanced performance and methods of forming the same

JC Costa, M Carroll - US Patent 12,057,374, 2024 - Google Patents
The present disclosure relates to a radio frequency device that includes a transfer device die
and a multilayer redistribution structure underneath the transfer device die. The transfer …

Ultrathin strained-SOI by stress balance on compliant substrates and FET performance

H Yin, KD Hobart, RL Peterson, FJ Kub… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Ultrathin, strained-silicon-on-insulator (s-SOI) structures without a residual silicon-
germanium (SiGe) underlayer have been fabricated using stress balance of bi-layer …