Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …

Aggressive process scaling and increasing demands of performance/cost efficiency have
exacerbated the incidences and impact of errors in DRAM systems. Due to this …

GPUs are used in high-reliability systems, including high-performance computers and
autonomous vehicles. Because GPUs employ a high-bandwidth, wide-interface to DRAM …

DRAM row and column sparing cannot efficiently tolerate the increasing inherent fault rate
caused by continued process scaling. In-DRAM ECC (IECC), an appealing alternative to …

This paper presents Turnstile, a hardware/software cooperative technique for low-cost soft
error resilience. Leveraging the recent advance of acoustic sensor based soft error …

Residue codes have been traditionally used for compute error correction rather than storage
error correction. In this paper, we use these codes for storage error correction with surprising …

Improvements in main memory storage density are primarily driven by process technology
scaling, which negatively impacts reliability by exacerbating various circuit-level error …

Emerging high-density non-volatile random access memories (NVRAMs) can significantly
enhance server main memory by providing both higher memory density and fast persistent …

Lung cancer is one of the most common malignant tumors leading to death. Early diagnosis
of pulmonary nodules is of great significance for reducing the mortality of the lung cancer …

As DRAM process technology scales down and DRAM density continues to grow, DRAM
errors have become a primary concern in modern data centers. Typically, data centers have …