In the past decades, advances in speed of commodity CPUs have far outpaced advances in
RAM latency. Main-memory access has therefore become a performance bottleneck for …

The major chip manufacturers have all introduced chip multiprocessing (CMP) and
simultaneous multithreading (SMT) technology into their processing units. As a result, even …

The holy grail for database architecture research is to find a solution that is Scalable &
Speedy, to run on anything from small ARM processors up to globally distributed compute …

Modern data center applications have rapidly expanding instruction footprints that lead to
frequent instruction cache misses, increasing cost and degrading data center performance …

Prior research shows that database system performance is dominated by off-chip data stalls,
resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels …

Fast access requirements preclude building L1 instruction caches large enough to capture
the working set of server workloads. Efforts exist to mitigate limited L1 instruction cache …

Modern data center applications have deep software stacks, with instruction footprints that
are orders of magnitude larger than typical instruction cache (I-cache) sizes. To efficiently …

L1 instruction-cache misses pose a critical performance bottleneck in commercial server
workloads. Cache access latency constraints preclude L1 instruction caches large enough …

L1 instruction fetch misses remain a critical performance bottleneck, accounting for up to
40% slowdowns in server applications. Whereas instruction footprints typically fit within last …

Modern processors employ a decoupled frontend with Fetch Directed Instruction Prefetching
(FDIP) to avoid frontend stalls in data center applications. However, the large branch …