Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large
increase in the size of on-chip caches. Since SRAM has low density and consumes large …

Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …

In recent years, embedded dynamic random-access memory (eDRAM) technology has been
implemented in last-level caches due to its low leakage energy consumption and high …

Abstract eDRAM cells have been considered as a promising alternative to conventional
SRAM cells and already adopted in commercial processors. However, eDRAM cells need to …

When the processor works at very-low voltages to save energy, failures in SRAM cells
increase exponentially at voltages below VCC min. In this context, current SRAM-error …

This book constitutes thoroughly refereed post-conference proceedings of the workshops of
the 19th International Conference on Parallel Computing, Euro-Par 2013, held in Aachen …

[EN] SRAM technology has traditionally been used to implement processor caches since it is
the fastest existing RAM technology. However, one of the major drawbacks of this …

When the processor works at very-low voltages to save energy, failures in SRAM cells
increase exponentially at voltages below V CCmin. In this context, current SRAM-error …

Unlike other previous techniques, the recently proposed Hard Error Recovery (HER) fault-
tolerant cache provides 100% fault-coverage in L1 data caches. This full coverage makes …