System, method, and computer program product for improving memory systems

MS Smith - US Patent 9,432,298, 2016 - Google Patents
H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …

Performance and energy analysis of the restricted transactional memory implementation on haswell

B Goel, R Titos-Gil, A Negi, SA McKee… - 2014 IEEE 28th …, 2014 - ieeexplore.ieee.org
Hardware transactional memory implementations are becoming increasingly available. For
instance, the Intel Core i7 4770 implements Restricted Transactional Memory (RTM) support …

Fault tolerance for multi-threaded applications by leveraging hardware transactional memory

G Yalcin, OS Unsal, A Cristal - … of the ACM International Conference on …, 2013 - dl.acm.org
Providing fault tolerance especially to mission critical applications in order to detect transient
and permanent faults and to recover from them is one of the main necessity for processor …

Detection of conflicts between transactions and page shootdowns

HW Cain III, HQ Le, B Lloyd, SH Tung - US Patent 9,086,987, 2015 - Google Patents
There is provided a system and a computer program product for detecting a conflict between
a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional …

Techniques to improve performance in requester-wins hardware transactional memory

A Armejach, R Titos-Gil, A Negi, OS Unsal… - ACM Transactions on …, 2013 - dl.acm.org
The simplicity of requester-wins Hardware Transactional Memory (HTM) makes it easy to
incorporate in existing chip multiprocessors. Hence, such systems are expected to be widely …

SEL-TM: Selective eager-lazy management for improved concurrency in transactional memory

L Zhao, W Choi, J Draper - 2012 IEEE 26th International …, 2012 - ieeexplore.ieee.org
Hardware Transactional Memory (HTM) systems implement version management and
conflict detection in hardware to guarantee that each transaction is atomic and executes in …

An adaptive fusion scheme of color and edge features for background subtraction

K Roy, J Kim, MTB Iqbal… - 2017 14th IEEE …, 2017 - ieeexplore.ieee.org
An adaptive fusion scheme of color and edge features for background subtraction Page 1
An Adaptive Fusion Scheme of Color and Edge Features for Background Subtraction …

DeTraS: Delaying stores for friendly-fire mitigation in hardware transactional memory

R Titos-Gil, R Fernández-Pascual… - … on Parallel and …, 2021 - ieeexplore.ieee.org
Commercial Hardware Transactional Memory (HTM) systems are best-effort designs that
leverage the coherence substrate to detect conflicts eagerly. Resolving conflicts in favor of …

[图书][B] Measurement, Modeling, and Characterization for Energy-efficient Computing

B Goel - 2016 - core.ac.uk
The ever-increasing ecological footprint of Information Technology (IT) sector coupled with
adverse effects of high power consumption on electronic circuits has increased the …

Transaction-Based Core Reliability

SWS Do, M Dubois - 2020 IEEE International Parallel and …, 2020 - ieeexplore.ieee.org
Modern microprocessor designs are becoming more vulnerable to transient faults leading to
transient errors due to design trends mandating low supply voltage and reduced noise …