Advances in semiconductor process and design technology enable the design of complex
system chips. Traditional IC design in which every circuit is designed from scratch and reuse …

This paper discusses the test strategies that can be employed for testing reusable
Intellectual Property (IP). A typical System on Chip (SoC) design carried out at ARM is …

A new core test wrapper design approach is proposed which transports streaming test data,
for example scan test patterns, into and out of an embedded core exclusively via (some of) …

This paper presents a design-for-debug (DfD) technique for network-on-chip (NoC)-based
system-on-chips (SoCs). We present a test wrapper and, a test and debug interface unit …

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to
meet short time-to-market requirements. However, the increasing cost of testing becomes a …

A test interface controller (TIC) provided by ARM Ltd. is widely used for functional testing of
system-on-a-chip (SoC) which adopts an advanced microcontroller bus architecture (AMBA) …

Test data travels through a System-on-Chip (SOC) from the chip pins to the module-under-
test and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is …

This work presents a testable design method for the embedded cores in an object SoC chip.
Instead of modifying the digital cores for testability consideration, we target on revising the …

Test scheduling and test access mechanism (TAM) design are two important tasks in the
development of a system-on-chip (SOC) test solution. Previous test scheduling techniques …

Conventional test access mechanism (TAM) and test wrappers of complex system-on-chip
(SoC) designs do not adequately utilize the system resources available in the functional …