A review and analysis of automatic optical inspection and quality monitoring methods in electronics industry

M Abd Al Rahman, A Mousavi - Ieee Access, 2020 - ieeexplore.ieee.org
Electronics industry is one of the fastest evolving, innovative, and most competitive
industries. In order to meet the high consumption demands on electronics components …

MLCAD: A survey of research in machine learning for CAD keynote paper

M Rapp, H Amrouch, Y Lin, B Yu… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

Advances in machine learning and deep learning applications towards wafer map defect recognition and classification: a review

T Kim, K Behdinan - Journal of Intelligent Manufacturing, 2023 - Springer
With the high demand and sub-nanometer design for integrated circuits, surface defect
complexity and frequency for semiconductor wafers have increased; subsequently …

Two-dimensional principal component analysis-based convolutional autoencoder for wafer map defect detection

J Yu, J Liu - IEEE Transactions on Industrial Electronics, 2020 - ieeexplore.ieee.org
Due to the high complexity and dynamics of the semiconductor manufacturing process,
various process abnormality could result in wafer map defects in many work stations. Thus …

A semi-supervised and incremental modeling framework for wafer map classification

Y Kong, D Ni - IEEE Transactions on Semiconductor …, 2020 - ieeexplore.ieee.org
Wafer map analysis provides critical information for quality control and yield improvement
tasks in semiconductor manufacturing. In particular, wafer patterns of gross failing areas …

Wafer map defect patterns classification using deep selective learning

MB Alawieh, D Boning, DZ Pan - 2020 57th ACM/IEEE Design …, 2020 - ieeexplore.ieee.org
With the continuous drive toward integrated circuits scaling, efficient yield analysis is
becoming more crucial yet more challenging. In this paper, we propose a novel …

A deep learning model for identification of defect patterns in semiconductor wafer map

Y Yuan-Fu - 2019 30th Annual SEMI Advanced Semiconductor …, 2019 - ieeexplore.ieee.org
The semiconductors are used as various precision components in many electronic products.
Each layer must be inspected of defect after drawing and baking the mask pattern in wafer …

Wafer map failure pattern recognition based on deep convolutional neural network

S Chen, Y Zhang, X Hou, Y Shang, P Yang - Expert Systems with …, 2022 - Elsevier
The objective of this paper is to propose a systematic failure pattern recognition for wafer
map based on neural networks. A deep convolutional neural network (DCNN) model which …

When wafer failure pattern classification meets few-shot learning and self-supervised learning

H Geng, F Yang, X Zeng, B Yu - 2021 IEEE/ACM International …, 2021 - ieeexplore.ieee.org
Due to advances in semiconductor processing technologies, wafer failure pattern detection
plays a key role in preventing yield loss excursion events for semiconductor manufacturing …

WDP-BNN: Efficient wafer defect pattern classification via binarized neural network

Q Zhang, Y Zhang, J Li, Y Li - Integration, 2022 - Elsevier
Wafer map defect pattern classification using convolutional neural network (CNN) has
gained a lot of attention in recent years but it demands huge computation and memory cost …