Report of the HPC Correctness Summit, Jan 25--26, 2017, Washington, DC

G Gopalakrishnan, PD Hovland, C Iancu… - arXiv preprint arXiv …, 2017 - arxiv.org
Maintaining leadership in HPC requires the ability to support simulations at large scales and
fidelity. In this study, we detail one of the most significant productivity challenges in …

Dynamic deadlock verification for general barrier synchronisation

T Cogumbreiro, R Hu, F Martins… - ACM Transactions on …, 2018 - dl.acm.org
We present Armus, a verification tool for dynamically detecting or avoiding barrier
deadlocks. The core design of Armus is based on phasers, a generalisation of barriers that …

Point-to-Point and Barrier Synchronization in Distributed SPMD Systems

S Milaković - 2019 - search.proquest.com
Distributed memory programming models are very often the only way to scale up large
scientific applications. To ensure correctness and optimal performance in distributed …

[PDF][PDF] Dynamic Deadlock Verification for General Barrier Synchronisation

R HU, F MARTINS, N YOSHIDA - 2018 - mrg.doc.ic.ac.uk
1 INTRODUCTION Dynamic verification of barrier deadlocks. The rise of multicore
processors and networked clusters has pushed mainstream programming languages to …

Report of the HPC Correctness Summit, January 25-26, 2017, Washington, DC

G Gopalakrishnan, PD Hovland, C Iancu… - 2017 - osti.gov
Technologies for verification and debugging have made significant strides in the context of
general systems software. An investment in such technologies to make them applicable for …

[引用][C] 1 DISSERTATION RESEARCH

KS Meel