A 44.3 TOPS/W SRAM compute-in-memory with near-CIM analog memory and activation for DAC/ADC-less operations
In this letter, we present an analog compute-in-memory (CIM) macro design which
incorporates near-CIM analog memory and nonlinearity activation unit (NAU) to alleviate the …
incorporates near-CIM analog memory and nonlinearity activation unit (NAU) to alleviate the …
Double MAC on a Cell: A 22-nm 8T-SRAM Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline
This paper proposes a novel 8T-SRAM based computing-in-memory (CIM) accelerator for
the Binary/Ternary neural networks. The proposed split dual-port 8T-SRAM cell has two …
the Binary/Ternary neural networks. The proposed split dual-port 8T-SRAM cell has two …
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin
D Kushwaha, RV Joshi, S Dasgupta… - … Symposium on Circuits …, 2024 - ieeexplore.ieee.org
This manuscript proposes an SRAM-based hybrid analog compute-in-memory (CIM)
architecture to enhance the signal margin. This hybrid architecture presents fully differential …
architecture to enhance the signal margin. This hybrid architecture presents fully differential …
GemIMC: A Configurable HW Architecture for Technology Agnostic IMC based NN Inference
E Taly, R Guizzetti, P Urard… - 2024 IFIP/IEEE 32nd …, 2024 - ieeexplore.ieee.org
This paper presents GemIMC, a High Level Synthesis (HLS) based configurable digital unit
architecture for accelerating Neural Networks (NN) at the edge using In Memory Computing …
architecture for accelerating Neural Networks (NN) at the edge using In Memory Computing …