CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

G Mahendran - Integration, 2024 - Elsevier
Abstract In modern Digital System design, adders are widely used in many applications
including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital …

[PDF][PDF] Design and leakage power optimization of 6T static random access memory cell using cadence virtuoso

S Banu, S Gupta - IJEER, 2022 - academia.edu
░ ABSTRACT-Reduction of Leakage power at nano meter regime has become a
challenging factor for VLSI designers. This is owing to the need for low-power, battery …

Design of energy-efficient full subtractor circuit at near threshold computing for signal processing application

MM Basha, S Gundala, V Madhurima… - Engineering Research …, 2024 - iopscience.iop.org
Energy Efficiency is a critical factor while designing integrated circuits. Therefore, a 1-bit full
subtractor (FS) cell is proposed for lower power application by employing Gate Level Body …

Leakage Minimization in Semiconductor Circuits for VLSI Application

S Banu, S Gupta - 2021 5th International Conference on …, 2021 - ieeexplore.ieee.org
Battery operated devices spend the majority of the time in standby mode (sleep mode).
Achieving the proper power dissipation especially leakage power has become a …

Single-Bit Architecture for Low Power IoT Applications

R Agrawal, S Singh, MKA Mohammed… - … Conference on Emerging …, 2022 - Springer
This paper discusses how six transistor static random access memory cells work, how a
write driver circuit works, and how different sense amplifiers work, like a current differential …

[PDF][PDF] Thermal Management Under Real-Time Constraints

B Ozceylan - 2023 - research.utwente.nl
Since its introduction by Gordon Moore in 1965, Moore's Law has served as a reliable
benchmark for predicting advancements in Integrated Circuit (IC) s. Moore's Law suggests …

Leakage Power Reduction in CMOS Inverter at 16 nm Technology

Y Sahu, AS Rajput, O Parmar, Z Mishra - International Conference on …, 2022 - Springer
As technology reduces to nm range, switching power, short-circuit power, and total power
consumption decrease, while leakage power consumption increases. There have been a …

[PDF][PDF] A LITERATURE SURVEY ON VLSI DESIGN FOR LOW POWER COMPLIMENTORY METAL OXIDE SEMICONDUTOR (CMOS) TECHNOLOGY

O SUDHAKAR, DRS KUMAR - researchgate.net
The design of low power circuits mainly focus on performance, power dissipation and chip
area. Low power is the real test for late hardware businesses. Control scattering is an …