A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length

VB Sreenivasulu, V Narendar - Silicon, 2021 - Springer
Abstract Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …

Design and temperature assessment of junctionless nanosheet FET for nanoscale applications

VB Sreenivasulu, V Narendar - Silicon, 2022 - Springer
Nanosheets are the revolutionary change to overcome the limitations of FinFET. In this
paper, the temperature dependence of 10 nm junctionless (JL) nanosheet FET performance …

Study and analysis of advanced 3D multi-gate junctionless transistors

R Kumar, S Bala, A Kumar - Silicon, 2022 - Springer
As the IC technology is evolving very rapidly, the feature size of the device has been
migrating to sub-nanometre regime for achieving the high packing density. To continue with …

Design and deep insights into sub-10 nm spacer engineered junctionless FinFET for nanoscale applications

N Vadthiya - ECS journal of solid state science and technology, 2021 - iopscience.iop.org
In this paper, we have studied the impact of various dielectric single-k (Sk) and dual-k (Dk)
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …

Junctionless gate-all-around nanowire FET with asymmetric spacer for continued scaling

VB Sreenivasulu, V Narendar - Silicon, 2021 - Springer
In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire
(NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC …

Circuit analysis and optimization of GAA nanowire FET towards low power and high switching

VB Sreenivasulu, V Narendar - Silicon, 2022 - Springer
The main aim of this work is to study the effect of symmetric and asymmetric spacer length
variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire …

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

J Debnath, MEH Sikder, S Singha - Engineering Research …, 2023 - iopscience.iop.org
In this work, a hetero-gate-oxide charge plasma-based nanowire transistor (HGO-CPNWT)
has been proposed, characterized, and a comparative analysis with the conventional charge …

Parameter variation analysis of dopingless and junctionless nanotube MOSFET

S Bala, R Kumar, A Kumar - Silicon, 2022 - Springer
In this paper, dopingless nanotube MOSFET (DL-NT MOSFET) has been designed for low
power circuit applications. Performance parameters of proposed device are extracted and …

Doping-less MultiGate Inverted-T shape FET device with Schottky source/drain contacts

S Munjal, NR Prakash, J Kaur - Microelectronics Journal, 2024 - Elsevier
A dopingless multi-gate inverted-T Shape device has been proposed with Schottky
source/drain contacts. Gate oxide engineering is performed on the proposed device, and its …

Design and simulation of a gas sensitive junctionless FinFET based on conducting polymer as the gate material

F Mehrdad, Z Ahangari - Physica Scripta, 2022 - iopscience.iop.org
In this study, we demonstrate a multi-gas sensing device utilizing junctionless Fin-shaped
Field Effect Transistor (FinFET) with conducting polymer as the gate material. The higher gas …