Research and Technologies for next-generation high-temperature data centers–State-of-the-arts and future perspectives
Data centers have attracted increasing attention worldwide over the last decades due to
their high energy consumption. Cooling accounts for about 30–40% of the total energy …
their high energy consumption. Cooling accounts for about 30–40% of the total energy …
Towards joint optimization over ICT and cooling systems in data centre: A survey
Effective management of ICT (information and communications technology) and cooling is
critical in modern data centres for high energy efficiency. This survey paper gives an …
critical in modern data centres for high energy efficiency. This survey paper gives an …
Memory errors in modern systems: The good, the bad, and the ugly
Several recent publications have shown that hardware faults in the memory subsystem are
commonplace. These faults are predicted to become more frequent in future systems that …
commonplace. These faults are predicted to become more frequent in future systems that …
Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …
latency is defined by three fundamental operations that take place within the DRAM cell …
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
In current systems, memory accesses to a DRAM chip must obey a set of minimum latency
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …
AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
Multirate refresh techniques exploit the non-uniformity in retention times of DRAM cells to
reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention …
reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention …
Fail-slow at scale: Evidence of hardware performance faults in large production systems
HS Gunawi, RO Suminto, R Sears, C Golliher… - ACM Transactions on …, 2018 - dl.acm.org
Fail-slow hardware is an under-studied failure mode. We present a study of 114 reports of
fail-slow hardware incidents, collected from large-scale cluster deployments in 14 …
fail-slow hardware incidents, collected from large-scale cluster deployments in 14 …
[图书][B] The datacenter as a computer: Designing warehouse-scale machines
LA Barroso, U Hölzle, P Ranganathan - 2019 - library.oapen.org
This book describes warehouse-scale computers (WSCs), the computing platforms that
power cloud computing and all the great web services we use every day. It discusses how …
power cloud computing and all the great web services we use every day. It discusses how …