Wafer level package using stud bump coated with solder

L Khor, YL Wai, LC Keong - US Patent 8,071,470, 2011 - Google Patents
A method of fabricated a wafer level package is described. In one embodiment, the method
includes fabricating at least one active device on a semiconductor wafer that has not been …

Electrically connecting substrate with electrical device

DM Craig, CH Chen - US Patent 7,476,608, 2009 - Google Patents
A substrate is electrically connected with an electrical device mounted on the substrate. A
ball bond is formed between a first end of a wire and a bonding pad of the substrate. A …

Electrically connecting substrate with electrical device

DM Craig, CH Chen - US Patent 7,576,439, 2009 - Google Patents
BACKGROUND Micro electro-mechanical systems (MEMS) devices are devices that
combine mechanical elements and electronic elements on a common substrate. MEMS …

Multi-chip package (MCP) with spacer

JB Shim, HS Hyun - US Patent 7,161,249, 2007 - Google Patents
A multi-chip package includes a substrate having first bonding pads and second bonding
pads, a first chip having chip pads on an active surface, spacers attached to the substrate …

Stacking structure for semiconductor chips and a semiconductor package using it

SG Lee, YH Kim, CH Lee - US Patent 6,982,485, 2006 - Google Patents
A semiconductor package and method of producing the same has a substrate having a resin
layer with first and second surfaces. A plurality of electrically conductive patterns are formed …

High-density wirebond chip interconnect for multi-chip modules

K Rush - US Patent 5,723,906, 1998 - Google Patents
As integrated circuits processing technology improves, an increasing number of devices and
functions can be inte grated onto a single chip. However, this creates a need for increasing …

Microstructure evolution of Ag–8Au–3Pd alloy wire during electromigration

R Guo, L Gao, M Li, D Mao, K Qian, H Chiu - Materials Characterization, 2015 - Elsevier
As the continuous shrinkage of the interconnect line width in microelectronics devices, there
is a growing concern about the electromigration (EM) failure of bonding wire. In addition, an …

Semiconductor package

SM Liou, C Liu - US Patent 8,022,522, 2011 - Google Patents
A semiconductor package is provided and methods for bonding wires in the semiconductor
package. In one implementation, the semiconductor package includes a lead frame …

Wire bonding process and wire bond structure

CC Lee - US Patent 6,561,411, 2003 - Google Patents
In a wire-bonding process, a chip is provided with at least a first contact pad. A chip carrier is
further provided with at least a second contact pad. A plurality of stacked conductive bumps …

Stitch bond enhancement for hard-to-bond materials

OF Torres, ER Hortaleza - US Patent 5,960,262, 1999 - Google Patents
A method of bonding a wire between a semiconductor die pad and a lead finger of a lead
frame which includes providing a capillary having a bore and a wire pigtail extending …