A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register

KS Kim, WS Yu, SH Cho - IEEE Journal of Solid-State Circuits, 2014 - ieeexplore.ieee.org
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For
pipelined operation, a novel time-register is proposed which is capable of storing, adding …

[图书][B] CMOS: front-end electronics for radiation sensors

A Rivetti - 2018 - books.google.com
CMOS: Front-End Electronics for Radiation Sensors offers a comprehensive introduction to
integrated front-end electronics for radiation detectors, focusing on devices that capture …

A 23μW solar-powered keyword-spotting ASIC with ring-oscillator-based time-domain feature extraction

K Kim, C Gao, R Graça, I Kiselev… - … Solid-State Circuits …, 2022 - ieeexplore.ieee.org
Voice-controlled interfaces on acoustic Internet-of-Things (IoT) sensor nodes and mobile
devices require integrated low-power always-on wake-up functions such as Voice Activity …

11.5 A time-correlated single-photon-counting sensor with 14GS/S histogramming time-to-digital converter

NAW Dutton, S Gnecchi, L Parmesan… - … Solid-State Circuits …, 2015 - ieeexplore.ieee.org
Time-correlated single photon counting (TCSPC) is a photon-efficient technique to record
ultra-fast optical waveforms found in numerous applications such as time-of-flight (ToF) …

A 20 Mb/s phase modulator based on a 3.6 GHz digital PLL with− 36 dB EVM at 5 mW power

G Marzin, S Levantino, C Samori… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
This paper presents a low-power high-bit-rate phase modulator based on a digital PLL with
single-bit TDC and two-point injection scheme. At high bit rates, this scheme requires a …

A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH -TDC for Low In-Band Phase Noise

Y Wu, M Shahmohammadi, Y Chen… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …

A noise-shaping time-to-digital converter using switched-ring oscillators—Analysis, design, and measurement techniques

A Elshazly, S Rao, B Young… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
A high-resolution time-to-digital converter (TDC) using switched-ring oscillators (SROs) is
presented. Leveraging oversampling and noise shaping, the proposed SRO-TDC achieves …

A CMOS SPAD sensor with a multi-event folded flash time-to-digital converter for ultra-fast optical transient capture

T Al Abbas, NAW Dutton, O Almer… - IEEE Sensors …, 2018 - ieeexplore.ieee.org
A digital silicon photomultiplier in 130-nm CMOS imaging technology implements time-
correlated single photon counting at an order of magnitude beyond the conventional pile-up …

An 11 b 7 ps resolution two-step time-to-digital converter with 3-D Vernier space

Y Kim, TW Kim - IEEE Transactions on Circuits and Systems I …, 2014 - ieeexplore.ieee.org
This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic
range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells …

digPLL-Lite: A low-complexity, low-jitter fractional-N digital PLL architecture

R Nonis, W Grollitsch, T Santa… - IEEE journal of solid …, 2013 - ieeexplore.ieee.org
This paper introduces a novel architecture of digital PLL. The goal of this architecture is to
reach low jitter, fractional operation, and FSK modulation capability with low architecture …